Granted Patent B2

US 8,514,687 · App. 12/915,829 · Granted Aug 20, 2013

Abstract

Claims (56)

1. A method of controlling crosstalk between channels of a communication system, comprising:

estimating crosstalk between channels of the system;

generating a compressed representation of the crosstalk estimates; and

generating compensated signals based on the compressed representation of the crosstalk estimates;

wherein the compressed representation comprises a value array and an index array, the value array comprising selected values from each of a plurality of rows of a matrix representation of the crosstalk estimates and the index array identifying locations of the selected values in the matrix representation of the crosstalk estimates.

2. The method of claim 1 wherein the step of generating compensated signals based on the compressed representation of the crosstalk estimates comprises generating pre-compensated signals.

3. The method of claim 2 further comprising the step of transmitting the pre-compensated signals from an access node of system to respective network terminals of the system over respective ones of the channels.

4. The method of claim 1 wherein the step of generating compensated signals based on the compressed representation of the crosstalk estimates comprises generating post-compensated signals.

5. The method of claim 4 further comprising the step of receiving uncompensated signals in an access node of the system from respective network terminals of the system over respective ones of the channels, wherein the post-compensated signals are generated from respective ones of the received uncompensated signals.

6. The method of claim 1 wherein the matrix representation of the crosstalk estimates is in the form of an N×N precoder or postcoder matrix, where N denotes the number of channels, and further wherein the N×N precoder or postcoder matrix is converted by a vector control entity into the compressed representation comprising the value array and the index array, each of which has N·m entries, where m is less than N and denotes a specified maximum number of dominant disturber channels for a given victim channel.

7. The method of claim 6 wherein the entries of the value array comprise complex values corresponding to respective ones of m selected crosstalk estimates from each of N rows of the precoder or postcoder matrix.

8. The method of claim 6 wherein the entries of the index array comprise scalar values denoting indices of respective ones of m selected crosstalk estimates from each of N rows of the precoder or postcoder matrix.

9. The method of claim 6 wherein at least one of the value array and the index array is in the form of a single row of length N·m.

10. The method of claim 6 wherein at least one of the value array and the index array is in the form of a matrix of dimension N×m.

11. The method of claim 2 wherein the step of generating pre-compensated signals further comprises performing the following operations:

for i= 0 to N− 1 do

for k=i·m to ( i+ 1)·( m− 1) do

y[i]=y[i]+C value[ k]·x[C index[ k]]

where N denotes the number of channels, m is less than N and denotes a specified maximum number of dominant disturber channels for a given victim channel, y is an N×1 vector of pre-compensated signals, x is a corresponding N×1 vector of signals prior to pre-compensation, Cvalue[k] denotes entry k in the value array of the compressed representation, and Cindex[k] denotes entry k in the index array of the compressed representation.

12. A non-transitory computer-readable storage medium having embodied therein executable program code that when executed by a processor of an access node of the system causes the access node to perform the steps of the method of claim 1 .

13. An apparatus comprising:

an access node configured to control crosstalk between channels of communication system;

wherein the access node comprises:

a plurality of transceivers; and

vectoring circuitry coupled to the transceivers;

the vectoring circuitry comprising a processor coupled to a memory and being operative to estimate crosstalk between the channels of the system, to generate a compressed representation of the crosstalk estimates, and to generate compensated signals based on the compressed representation of the crosstalk estimates;

wherein the compressed representation comprises a value array and an index array, the value array comprising selected values from each of a plurality of rows of a matrix representation of the crosstalk estimates and the index array identifying locations of the selected values in the matrix representation of the crosstalk estimates.

14. The apparatus of claim 13 wherein the access node comprises a DSL access multiplexer.

15. The apparatus of claim 13 wherein the vectoring circuitry comprises:

a vector control entity operative to estimate the crosstalk between the channels of the system and to generate the compressed representation of the crosstalk estimates; and

a vectoring signal processing module operative to generate the compensated signals based on the compressed representation of the crosstalk estimates.

16. The apparatus of claim 13 wherein the processor comprises a vector processor configured to generate the compensated signals.

17. The apparatus of claim 16 wherein the vector processor comprises:

a plurality of computation slices arranged in parallel with one another, one for each of the channels;

wherein each of the computation slices comprises:

first memory circuitry for storing entries of the index array;

second memory circuitry for storing entries of the value array;

third memory circuitry for storing entries of an uncompensated input signal vector and having a selection input coupled to an output of the first memory circuitry;

a complex multiply-accumulate unit having inputs coupled to outputs of the first and third memory circuitry; and

an output register having an input coupled to an output of the complex multiply-accumulate unit;

the computation slice generating entries of a compensated output signal vector.

18. The apparatus of claim 17 wherein the compressed representation is stored in an external memory of the vector processor under control of a vector control entity and portions of said representation are supplied to the first and second memory circuitry of the vector processor as needed for vectoring computations performed by the vector processor.

19. The apparatus of claim 17 wherein the vector processor is implemented in the form of a single integrated circuit.

20. A communication system comprising the apparatus of claim 13 .

21. An integrated circuit comprising:

a vector processor operative to generate compensated signals based on a compressed representation of estimates of crosstalk between channels of a communication system;

wherein the compressed representation comprises a value array and an index array, the value array comprising selected values from each of a plurality of rows of a matrix representation of the crosstalk estimates and the index array identifying locations of the selected values in the matrix representation of the crosstalk;

wherein the vector processor comprises:

a plurality of computation slices arranged in parallel with one another, one for each of the channels;

wherein each of the computation slices comprises:

first memory circuitry for storing entries of the index array;

second memory circuitry for storing entries of the value array;

third memory circuitry for storing entries of an uncompensated input signal vector and having a selection input coupled to an output of the first memory circuitry;

a complex multiply-accumulate unit having inputs coupled to outputs of the first and third memory circuitry; and

an output register having an input coupled to an output of the complex multiply-accumulate unit;

the computation slice generating entries of a compensated output signal vector.

Assignments (12)