Apparatus for time to digital conversion
View Patent ↗A time-to-digital converter device includes a first delay chain circuit that generates a first value corresponding to a time delay between a start signal and a stop signal. The time-to-digital converter device also includes at least one second delay chain circuits that generates a second value corresponding to a time delay between a delayed start signal and the stop signal. At least one delay element generates the delayed start signal by applying a predetermined delay to the start signal, and a combining circuit generates an output value based on the first and second values. In the time-to-digital converter according to the exemplary embodiments of the present advancements, the output value corresponds to the time delay between the start signal and the stop signal.
1. A time-to-digital converter device, comprising:
a first delay chain circuit configured to generate a first value corresponding to a time delay between a start signal and a stop signal;
at least one second delay chain circuit configured to generate a second value corresponding to a time delay between a delayed start signal and the stop signal;
at least one delay element configured to generate the delayed start signal by applying a predetermined delay to the start signal; and
a combining circuit configured to generate an output value based on the first and second values, the output value corresponding to the time delay between the start signal and the stop signal.
2. The time-to-digital converter device, according to claim 1 , wherein each of the first and the at least one second delay chain circuits includes
a delay chain having a plurality of delay chain elements, each delay chain element providing a same predetermined delay, the start signal being provided to the delay chain;
a plurality of memory elements, each connected to one of the plurality of delay elements in the delay chain, the plurality of memory elements having a common clock input to receive the stop signal; and
a decoder circuit configured to generate digital values based on outputs of the plurality of memory elements.
3. The time-to-digital converter device according to claim 2 , wherein the decoder circuit is a thermometer decoder.
4. The time-to-digital converter device according to claim 2 , wherein the predetermined delay of the delay element is inversely proportional to a number of delay chain circuits included in the time-to-digital converter device.
5. The time-to-digital converter device according to claim 1 , wherein each of the first and the at least one second delay chain circuit are Vernier time-to-digital conversion circuits.
6. The time-to-digital converter device according to claim 1 , wherein the combining circuit is an adder.
7. The time-to-digital converter device according to claim 1 , wherein the combining circuit is an averager.
8. A method of improving the resolution of a time-to-digital converter device, comprising:
generating, at a first time-to-digital converter, a first value indicating a time delay between a start signal and a stop signal;
delaying the start signal by at least one predetermined delay;
generating at least one second value indicating a time delay between the delayed start signal and the stop signal; and
combining the first and second values into an output value indicative of the time delay between the start signal and the stop signal.
9. The method according to claim 8 , wherein each of generating the first value and generating the at least one second value includes
delaying the start signal in a delay chain including a plurality of delay chain elements;
capturing outputs of each of the delay chain elements in a plurality of memory elements in response to the stop signal; and
generating digital values based on outputs of the plurality of memory elements.
10. The method according to claim 9 , wherein the digital values are generated according to a thermometer decoder algorithm.
11. The method according to claim 9 , wherein the delaying step includes delaying the start signal by an inverse number of first and second values to be generated.
12. The method according to claim 8 , wherein the combining step includes adding the first and second values.
13. The method according to claim 8 , wherein the combining step includes averaging the first and second values.
14. A gamma ray detection system, comprising:
a plurality of scintillation crystals configured to generate scintillation light in response to interaction with a gamma ray;
a plurality of photomultiplier tubes arranged to detect the scintillation light generated by the scintillation crystals, the plurality of photomultiplier tubes generating a detection signal in response to detection of the scintillation light;
a time-to-digital converter configured to determine a time of arrival of the gamma ray, the time-to-digital converter including
a first delay chain circuit configured to generate a first value corresponding to a time delay between a start signal and a stop signal corresponding to edges of the detection signal,
at least one second delay chain circuits configured to generate a second value corresponding to a time delay between a delayed start signal and the stop signal,
at least one delay element configured to generate the delayed start signal by applying a predetermined delay to the start signal, and
a combining circuit configured to generate an output value based on the first and second values, the output value corresponding to the time of arrival of the gamma ray.