Double data rate interface
View Patent ↗The present invention relates to a double data rate interface and method for use between a processor and random access memory, comprising a delay line including means for creating a delay in a data strobe signal from the random access memory, the delay line being arranged such that the delay in the data strobe signal is equal to the sum of set-up time and data bus rise time. The interface of includes the delay line comprising the delay locked loop which in turn comprises a ring oscillator. The ring oscillator includes a buffer and a Vernier delay.
1. An electronic circuit for a double data rate interface arranged between a processor and random access memory, the electronic circuit comprising:
an element that creates a first delay in a first data strobe signal from the random access memory and a second delay in a second data strobe signal from the random access memory,
wherein the first and the second data strobe signal are each others complement, the electronic circuit being arranged such that the respective delays in the respective data strobe signals are equal to a sum of a set-up time and a data bus rise time,
wherein the electronic circuit further comprises:
a controller,
a first slave delay line for delaying the first data strobe signal with the first delay,
a second slave delay line for delaying the second data strobe signal with the second delay, wherein the first slave delay line and the second slave delay line comprise variable delay line elements that are also controlled by the controller, and
a delay-locked loop, wherein the delay-locked loop comprises a terminal for receiving a clock signal, a delay line coupled to the terminal for delaying the clock signal to obtain a delayed clock, wherein the delay line comprises a plurality of variable delay line elements, the delay-locked loop further comprising: i) a phase comparator for comparing the delayed clock with the clock signal, and ii) the controller for controlling respective delays of the plurality of variable delay line elements to obtain a phase difference between of clock signal and the delayed clock of one clock period of the reference clock, and wherein the first and second delays of the plurality of delay line elements of the respective slave delay lines is matched with the sum of the set-up time and data bus rise time.
2. The electronic circuit as in claim 1 , further comprising:
a ring oscillator for forming a ring oscillator signal, the ring oscillator comprising a plurality of variable delay line elements, the electronic circuit further comprising a first divider and a second divider, wherein the first divider and the second divider are programmable, the first divider being coupled to an output of the ring oscillator for dividing the ring oscillator signal, the second divider being coupled between the terminal and the phase comparator for dividing the clock signal, the first divider and the second divider being coupled with their output to a phase comparator, the phase comparator being coupled to the controller, wherein the controller is also coupled to the plurality of variable delay line elements of the ring oscillator for controlling a stage delay of the ring oscillator and thereby a ring oscillator frequency, the electronic circuit further comprising means for programming the first and second dividers to vary a ratio therebetween so as to obtain a delay of the respective slave delay lines that is a fraction of the clock period and that is matched with the sum of set-up time and data bus rise time.
3. The electronic circuit as in claim 2 , further comprising a buffer within the ring oscillator for driving the first divider.
4. The electronic circuit as in claim 3 , wherein the respective slave delay lines include a buffer.
5. The electronic circuit as in claim 3 , wherein the buffer is arranged to compensate for an extra delay required to drive a fast clock edge.
6. The electronic circuit as in claim 2 , wherein the delay line in the oscillator and the respective slave delay lines comprise numbers of groups of individual variable delay line elements such that the delays implemented in the oscillator and in the slave delay lines have an integer ratio time value relationship.
7. A double data rate interface arranged between a processor and a random access memory, the double data rate interface comprising the circuit as in claim 1 .
8. A processor including a double data rate interface as in claim 7 .
9. A processor as in claim 8 , wherein the data transfer interface comprises a data bus.
10. A method of double data rate transfer between a processor and a random access memory whereby an electronic circuit creates a first delay in a first data strobe signal from said random access memory and a second delay in a second data strobe signal from the random access memory, wherein the first and the second data strobe signal are each others complement, the method including a step of individually delaying the respective data strobe signals by a period substantially equal to a sum of a set-up time and a data bus rise time,
wherein the step of individually delaying the respective data strobe signals includes delaying the first data strobe signal with the first delay using a first slave delay line and delaying the second data strobe signal with the second delay using a second slave delay line, wherein the first slave delay line and the second slave delay line comprise variable delay line elements that are also controlled by a controller,
the method further including;
receiving a clock signal at a terminal of a delay-locked loop,
delaying the clock signal to obtain a delayed clock using a delay line of the delay-locked loop that is coupled to the terminal, wherein the delay line comprises a plurality of variable delay line elements,
comparing the delayed clock with the clock signal using a phase comparator of the delay-locked loop, and
controlling respective delays of the plurality of variable delay line elements using the controller to obtain a phase difference between of clock signal and the delayed clock of one clock period of the reference clock,
wherein the first and second delays of the plurality of delay line elements of the respective slave delay lines is matched with the sum of the set-up time and data bus rise time.
11. An electronic circuit for a double data rate interface arranged between a processor and random access memory, the electronic circuit comprising:
an element that creates a first delay in a first data strobe signal from the random access memory and a second delay in a second data strobe signal from the random access memory,
wherein the first and the second data strobe signal are each others complement, the electronic circuit being arranged such that the respective delays in the respective data strobe signals are equal to a sum of a set-up time and a data bus rise time,
wherein the electronic circuit further comprises:
a controller,
a first slave delay line for delaying the first data strobe signal with the first delay,
a second slave delay line for delaying the second data strobe signal with the second delay, wherein the first slave delay line and the second slave delay line comprise variable delay line elements that are also controlled by the controller, and
a ring oscillator for forming a ring oscillator signal, the ring oscillator comprising a plurality of variable delay line elements, the electronic circuit further comprising a first divider and a second divider, wherein the first divider and the second divider are programmable, the first divider being coupled to an output of the ring oscillator for dividing the ring oscillator signal, the second divider being coupled between the terminal and the phase comparator for dividing the clock signal, the first divider and the second divider being coupled with their output to a phase comparator, the phase comparator being coupled to the controller, wherein the controller is also coupled to the plurality of variable delay line elements of the ring oscillator for controlling a stage delay of the ring oscillator and thereby a ring oscillator frequency, the electronic circuit further comprising means for programming the first and second dividers to vary a ratio therebetween so as to obtain a delay of the respective slave delay lines that is a fraction of the clock period and that is matched with the sum of set-up time and data bus rise time.
12. The electronic circuit of claim 11 , further comprising a buffer within the ring oscillator for driving the first divider.
13. The electronic circuit of claim 12 , wherein the respective slave delay lines include a buffer.
14. The electronic circuit of claim 12 , wherein the buffer is arranged to compensate for an extra delay required to drive a fast clock edge.
15. The electronic circuit of claim 11 , wherein the delay line in the oscillator and the respective slave delay lines comprise numbers of groups of individual variable delay line elements such that the delays implemented in the oscillator and in the slave delay lines have an integer ratio time value relationship.