Hysteresis-compensating interpolation circuits in optical encoders
View Patent ↗Disclosed are various embodiments of circuitry and methods to compensate for variations in hysteresis associated with the comparators of an interpolation circuit in a single track optical encoder. Such variations in hysteresis may be minimized or eliminated by providing appropriately configured resistor ladder circuits to condition the inputs to the comparators, or by programming or trimming resistors in positive feedback loops of the comparators. The single track optical encoder configurations disclosed herein permit very high resolution reflective optical encoders in small packages to be provided. Methods of making and using such optical encoders are also disclosed.
1. A high resolution, high speed, single track optical encoder, comprising:
a light emitter configured to emit light therefrom;
a plurality of photodetectors or photodiodes having leading and trailing edges arranged along a single track and a common axis to form a single track light detector, the single track light detector having disposed along the common axis pairs of A and A\ data channel light detectors and B and B\ data channel light detectors, the A and B light detectors, and the A\ and B\ light detectors, respectively, being arranged to generate output signals that are 90 degrees out of phase with respect to one another, the A, A\, B and B\ light detectors generating respective first, second, third and fourth output ramp signals;
signal generation circuitry comprising at least first, second, third and fourth amplifiers configured to receive as inputs thereto, respectively, the first, second, third and fourth output ramp signals corresponding to the A, A\, B and B\ light detectors, the first amplifier being configured to provide full A and fractional A output ramp signals, the second amplifier being configured to provide full A\ and fractional A\ output ramp signals, the third amplifier being configured to provide full B and fractional B output ramp signals, the fourth amplifier being configured to provide full B\ and fractional B\ output ramp signals;
a first set of first, second, third and fourth resistor ladders configured to receive the full A and fractional A output ramp signals, full A\ and fractional A\ output ramp signals, the B and fractional B output ramp signals, and the full B\ and fractional B\ output ramp signals, respectively, as input signals thereto, respectively, each of the first, second, third and fourth resistor ladders having resistor values associated therewith such that intermediate output signals provided by each of the resistor ladders all have substantially the same slope or complementary slope at any given time;
a first comparator configured to receive the A and fractional A intermediate output signals, a second comparator configured to receive the A\ and fractional A\ intermediate output signals, a third comparator configured to receive the B and fractional B intermediate output signals, and a fourth comparator configured to receive the B\ and fractional B\ intermediate output signals as inputs thereto, the first, second, third and fourth comparators providing intermediate first, second, third and fourth output signals therefrom, respectively, and
logic circuitry configured to receive the resistor ladder output signals and generate channel A and channel B output square wave or pulse signals on the basis of the resistor ladder output signals;
wherein the first set of first, second, third and fourth resistor ladders have resistor values associated therewith such that the intermediate output signals provided by each of the resistor ladders all have substantially the same slope or complementary slope at any given time and thereby eliminate differences in hysteresis between the first, second, third and fourth comparators.
2. The high resolution, high speed, single track optical encoder of claim 1 , further comprising a second set of first, second, third and fourth tunable resistor ladders configured to receive the intermediate first, second, third and fourth output signals as input signals thereto, respectively, each of the first, second, third and fourth resistor ladders of the second set of resistor ladders having tunable resistances associated therewith that may be selected by first, second, third and fourth control signals delivered thereto, respectively, such that output signals provided by each of the resistor ladders all have substantially the same slope or complementary slope at any given time.
3. The high resolution, high speed, single track optical encoder of claim 1 , further comprising a second set of first, second, third and fourth tunable resistor ladders configured to receive the intermediate first, second, third and fourth output signals as input signals thereto, respectively, each of the first, second, third and fourth resistor ladders of the second set of resistor ladders having trimmable resistances associated therewith that may be selected, respectively, such that output signals provided by each of the resistor ladders all have substantially the same slope or complementary slope at any given time.
4. The high resolution, high speed, single track optical encoder of claim 1 , wherein at least some of the fractional output ramp signals correspond to about one-third the amplitude of the full output ramp signals.
5. The high resolution, high speed, single track optical encoder of claim 1 , wherein at least some of the fractional output ramp signals correspond to about one-sixth the amplitude of the full output ramp signals.
6. The high resolution, high speed, single track optical encoder of claim 1 , wherein the signal generation circuitry, the comparators and the logic circuitry are implemented in a CMOS device.
7. The high resolution, high speed, single track optical encoder of claim 1 , wherein the signal generation circuitry, the comparators and the logic circuitry are implemented in a BiCMOS device.
8. The high resolution, high speed, single track optical encoder of claim 1 , wherein the signal generation circuitry, the comparators and the logic circuitry are implemented in a semiconductor integrated circuit device.
9. The high resolution, high speed, single track optical encoder of claim 1 , wherein the hysteresis of the comparators ranges between about 10 mV and about 50 mV.
10. The high resolution, high speed, single track optical encoder of claim 1 , wherein the photodetectors or photodiodes are arranged along the single track and the common axis to form a sequential pattern or a repeating sequential pattern of photodetectors or photodiodes defined by one of (A, B, A\, B\), (A, A\, B, B\), (A, B\, A\, B) or (A, B, A\, B\).
11. Circuitry for use in connection with an optical encoder, the circuitry comprising:
a plurality of photodetectors or photodiodes having leading and trailing edges arranged along a single track and a common axis to form a single track light detector, the single track light detector having disposed along the common axis pairs of A and A\ data channel light detectors and B and B\ data channel light detectors, the A and B light detectors, and the A\ and B\ light detectors, respectively, being arranged to generate output signals that are 90 degrees out of phase with respect to one another, the A, A\, B and B\ light detectors generating respective first, second, third and fourth output ramp signals;
signal generation circuitry comprising at least first, second, third and fourth amplifiers configured to receive as inputs thereto, respectively, the first, second, third and fourth output ramp signals corresponding to the A, A\, B and B\ light detectors, the first amplifier being configured to provide full A and fractional A output ramp signals, the second amplifier being configured to provide full A\ and fractional A\ output ramp signals, the third amplifier being configured to provide full B and fractional B output ramp signals, the fourth amplifier being configured to provide full B\ and fractional B\ output ramp signals;
a first set of first, second, third and fourth resistor ladders configured to receive the full A and fractional A output ramp signals, full A\ and fractional A\ output ramp signals, the B and fractional B output ramp signals, and the full B\ and fractional B\ output ramp signals, respectively, as input signals thereto, respectively, each of the first, second, third and fourth resistor ladders having resistor values associated therewith such that intermediate output signals provided by each of the resistor ladders all have substantially the same slope or complementary slope at any given time;
a first comparator configured to receive the A and fractional A intermediate output signals, a second comparator configured to receive the A\ and fractional A\ intermediate output signals, a third comparator configured to receive the B and fractional B intermediate output signals, and a fourth comparator configured to receive the B\ and fractional B\ intermediate output signals as inputs thereto, the first, second, third and fourth comparators providing intermediate first, second, third and fourth output signals therefrom, respectively, and
logic circuitry configured to receive the resistor ladder output signals and generate channel A and channel B output square wave or pulse signals on the basis of the resistor ladder output signals;
wherein the first set of first, second, third and fourth resistor ladders have resistor values associated therewith such that the intermediate output signals provided by each of the resistor ladders all have substantially the same slope or complementary slope at any given time and thereby eliminate differences in hysteresis between the first, second, third and fourth comparators.
12. The circuitry of claim 11 , wherein at least some of the fractional output ramp signals correspond to about one-third the amplitude of the full output ramp signals.
13. The circuitry of claim 11 , wherein at least some of the fractional output ramp signals correspond to about one-sixth the amplitude of the full output ramp signals.
14. The circuitry of claim 11 , wherein the signal generation circuitry, the comparators and the logic circuitry are implemented in a CMOS device.
15. The circuitry of claim 11 , wherein the signal generation circuitry, the comparators and the logic circuitry are implemented in a BiCMOS device.
16. The circuitry of claim 11 , wherein the signal generation circuitry, the comparators and the logic circuitry are implemented in a semiconductor integrated circuit device.
17. The circuitry of claim 11 , further comprising a second set of first, second, third and fourth tunable resistor ladders configured to receive the intermediate first, second, third and fourth output signals as input signals thereto, respectively, each of the first, second, third and fourth resistor ladders of the second set of resistor ladders having tunable resistances associated therewith that may be selected by first, second, third and fourth control signals delivered thereto, respectively, such that output signals provided by each of the resistor ladders all have substantially the same slope or complementary slope at any given time.
18. The circuitry of claim 11 , wherein further comprising a second set of first, second, third and fourth tunable resistor ladders configured to receive the intermediate first, second, third and fourth output signals as input signals thereto, respectively, each of the first, second, third and fourth resistor ladders of the second set of resistor ladders having trimmable resistances associated therewith that may be selected, respectively, such that output signals provided by each of the resistor ladders all have substantially the same slope or complementary slope at any given time.
19. The circuitry of claim 11 , wherein the photodetectors or photodiodes are arranged along the single track and the common axis to form a sequential pattern or a repeating sequential pattern of photodetectors or photodiodes defined by one of (A, B, A\, B\), (A, A\, B, B\), (A, B\, A\, B) or (A, B, A\, B\).