IP Library Granted Patent US 8,525,760
Granted Patent B2
US 8,525,760 · App. 12/917,885 · Granted Sep 3, 2013

Active matrix substrate, electro-optical device, and electronic device

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Quick Facts
Patent No.
US 8,525,760
App. No.
12/917,885
Granted
Sep 3, 2013
Kind
B2
Abstract

An active matrix substrate is provided which does not cause reductions in the brightness of electroluminescence elements, and which comprises appropriate peripheral circuitry occupying a small area. The active matrix substrate comprises peripheral circuits to supply current to EL elements provided for each pixel, and corresponding to EL elements, and further comprises a holding element (C) which holds a control voltage, a first active element (T 1 ) connected to the holding element (C) and which supplies current to a light-emitting portion (OLED) based on a control voltage, and a second active element (T 2 ) connected to the holding element (C) and which controls the charging and discharging of the holding element. In particular, the second active element (T 2 ) is configured as a multiple-control-terminal type active element. As a result, there are no fluctuations in the programmed current.

Claims (28)

1. An electro-optical device comprising:

a data line;

a control line; and

a unit circuit arranged corresponding to an intersection of the data line and the control line, the unit circuit including:

a first transistor that includes a first semiconductor film;

an electro-optical element electrically connected to one of a source or a drain of the first transistor;

a second transistor that includes a second semiconductor film, the second transistor connected between the one of the source or the drain and a gate of the first transistor;

a holding element that is connected to the gate of the first transistor and holds a gate voltage of the first transistor according to a data signal; and

a wiring connected between the second transistor and the gate of the first transistor,

the first transistor supplying a current based on the gate voltage to the electro-optical element,

the wiring being formed in a layer which is different from a layer in which the first semiconductor film and the second semiconductor film are formed,

the wiring having a portion formed in the layer different from a gate layer in which the gate of the first transistor is formed, the portion crossing the control line.

2. The electro-optical device according to claim 1 , wherein the first transistor has a conduction type different from a conduction type the second transistor has.

3. An electric device comprising an electro-optical device according to claim 2 .

4. The electro-optical device according to claim 1 , wherein the control line supplies a control signal to a gate of the second transistor.

5. The electro-optical device according to claim 4 ,

wherein the unit circuit further includes a third transistor coupled between the holding element and the data line, and

wherein the second transistor and the third transistor are controlled according to the control signal.

6. An electric device comprising an electro-optical device according to claim 5 .

7. An electric device comprising an electro-optical device according to claim 4 .

8. An electric device comprising an electro-optical device according to claim 1 .

9. The electro-optical device according to claim 1 , further comprising a power line, the power line being formed in a layer in which the data line and the wiring are formed.

10. The electro-optical device according to claim 9 ,

wherein the first transistor has a first terminal, a second terminal, and a channel region disposed between the first terminal and the second terminal, the first terminal being disposed between the power line and the second terminal, and

the first transistor controlling an electrical connection between the first terminal and the second terminal.

11. The electro-optical device according to claim 9 ,

wherein the first transistor has a first terminal, a second terminal, and a channel region disposed between the first terminal and the second terminal, the first terminal being disposed between the power line and the second terminal, and

the first transistor controlling an electrical connection between the first terminal and the second terminal.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2022
From: EL TECHNOLOGY FUSION GODO KAISHA
To: ELEMENT CAPITAL COMMERCIAL COMPANY PTE. LTD.
Reel/Frame 059431/0845 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 17, 2022
From: EL TECHNOLOGY FUSION GODO KAISHA
To: ELEMENT CAPITAL COMMERCIAL COMPANY PTE. LTD.
Reel/Frame 059912/0458 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2018
From: SEIKO EPSON CORPORATION
To: EL TECHNOLOGY FUSION GODO KAISHA
Reel/Frame 047998/0879 →