Display apparatus
View Patent ↗There is a need for decreasing a variation in times for writing to TFT elements for pixels in a direction along the extension of a gate line in a liquid crystal display apparatus. A display apparatus includes a display panel having multiple gate lines and multiple drain lines arranged in a matrix and a data driver for outputting a display data signal to each drain line. The data driver includes: an internal control signal generation circuit for generating an internal control signal for setting a timing to output a data signal to a drain line of each block on a block basis by dividing the plurality of drain lines into multiple blocks; and a register circuit for recording a setting for division of the block, a setting for a delay direction and a delay width of a timing to output the data signal, and a setting for rising and falling of an internal control signal.
1. A display apparatus comprising:
a display panel having a plurality of gate lines and a plurality of drain lines arranged in a matrix;
a scanning driver for outputting a scanning signal to each gate line;
a data driver for outputting a display data signal to each drain line; and
a display control circuit for controlling a timing to output a scanning signal from the scanning driver and a timing to output a data signal from the data driver,
wherein the scanning driver includes a level shifter circuit for converting a signal level of an output signal from a shift register circuit,
wherein the level shifter circuit includes a first circuit unit operating on a low-voltage power supply and a second circuit unit operating on a high-voltage power supply,
wherein the first circuit unit includes a latch circuit for temporarily holding an input signal; and
wherein the second circuit unit includes at least two P-channel MOS transistors and two N-channel MOS transistors;
wherein a first N-channel MOS transistor allows a gate electrode to be connected with a first output terminal of the first circuit unit and allows a drain electrode to be connected with a drain electrode of a first P-channel MOS transistor and with a gate electrode of a second P-channel MOS transistor;
wherein a second N-channel MOS transistor allows a gate electrode to be connected with a second output terminal of the first circuit unit and allows a drain electrode to be connected with a drain electrode of a second P-channel MOS transistor and with a gate electrode of a first P-channel MOS transistor,
wherein the first circuit unit comprises a third P-channel MOS transistor, a third N-channel MOS transistor, a fourth N-channel MOS transistor, and a fifth N-channel MOS transistor,
wherein the third P-channel MOS transistor allows a gate electrode to be connected with an input terminal for an input signal based on an output from the shift register circuit and a first enable signal,
wherein the third N-channel MOS transistor allows a gate electrode to be connected with an input terminal for a second enable signal and allows a drain electrode to be connected with a drain electrode of the third P-channel MOS transistor and a gate electrode of the fourth N-channel MOS transistor via a NOT gate,
wherein the fourth N-channel MOS transistor allows a source electrode to be connected with a drain electrode of the third P-channel MOS transistor,
wherein the fifth N-channel MOS transistor allows a gate electrode to be connected with an input terminal of a third enable signal and allows a drain electrode to be connected with a drain electrode of the fourth N-channel MOS transistor,
wherein the first output terminal is connected with a drain electrode of the third P-channel MOS transistor, and
wherein the second output terminal is connected, via a NOT gate, with a stage subsequent to a node between a drain electrode of the third P-channel MOS transistor and a source electrode of the fourth N-channel MOS transistor.
2. The display apparatus according to claim 1 , wherein a differential amplifier circuit generates the second and third enable signals.