Semiconductor device
View Patent ↗A semiconductor device has an external connection terminal, an internal circuit region, an ESD protection N-MOS transistor provided between the external connection terminal and the internal circuit region to protect an internal element formed in the internal circuit region, and a shallow trench structure provided to isolate the ESD protection N-MOS transistor. A thin insulating film is formed on a drain region of the ESD protection N-MOS transistor. An electrode is disposed above the drain region and on the thin insulating film for receiving a signal from the external connection terminal. The thin insulating film has a film thickness and film properties that allow dielectric breakdown and establish conduction between the electrode and the drain region when a voltage exceeding an absolute maximum rating of the semiconductor device is applied to the electrode.
1. A semiconductor device, comprising:
an external connection terminal;
an internal circuit region;
an ESD protection N-MOS transistor provided between the external connection terminal and the internal circuit region to protect an internal element formed in the internal circuit region;
a shallow trench structure provided to isolate the ESD protection N-MOS transistor;
a thin insulating film formed on a drain region of the ESD protection N-MOS transistor; and
an electrode disposed above the drain region and on the thin insulating film for receiving a signal from the external connection terminal;
wherein the thin insulating film has a film thickness and film properties that allow dielectric breakdown and establish conduction between the electrode and the drain region when a voltage exceeding an absolute maximum rating of the semiconductor device is applied to the electrode.
2. A semiconductor device according to claim 1 , wherein the electrode is formed of a polysilicon film.
3. A semiconductor device according to claim 1 , wherein the electrode is formed of the same film as is used for a gate electrode of a MOS transistor in the internal circuit region.
4. A semiconductor device according to claim 1 , wherein the thin insulating film is formed of a silicon oxide film.
5. A semiconductor device according to claim 1 , wherein the thin insulating film is formed of a composite film of a silicon oxide film and a silicon nitride film.
6. A semiconductor device comprising:
an external connection terminal;
an internal circuit region;
an ESD protection N-MOS transistor provided between the external connection terminal and the internal circuit region to protect an internal element formed in the internal circuit region;
a shallow trench structure provided to isolate the ESD protection N-MOS transistor;
a thin insulating film formed on a drain region of the ESD protection N-MOS transistor, the thin insulating film being formed of the same film as is used for a tunnel oxide film of an EEPROM formed in the internal circuit region; and
an electrode disposed above the drain region and on the thin insulating film for receiving a signal from the external connection terminal.
7. A semiconductor device according to claim 1 , wherein the ESD protection N-MOS transistor has an LDD structure.
8. A semiconductor device according to claim 1 , wherein the ESD protection
N-MOS transistor has an offset drain structure.