Semiconductor device with non-volatile memory and random access memory
View Patent ↗A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.
1. A controller for use with a flash memory and a dynamic random access memory, the controller comprising:
a command register,
wherein the controller controls the flash memory and the dynamic random access memory to transfer data from the flash memory to the dynamic random access memory when a load instruction is written into the command register from an outside of the controller.
2. A controller according to claim 1 , further comprising:
a terminal outputting a signal during transferring the data from the flash memory to the dynamic random access memory.
3. A controller according to claim 1 ,
wherein the dynamic random access memory is a SDARM.
4. A controller according to claim 1 ,
wherein the dynamic random access memory is a DDR-SDARM, and
wherein the controller further includes:
a clock input terminal receiving a first clock signal, and
a clock output terminal providing a second clock signal based on the first clock signal to the DDR-SDRAM.
5. A controller according to claim 1 ,
wherein the flash memory is a NAND type flash memory.
6. A controller for use with a flash memory and a DRAM synchronized with a clock, the controller comprising:
a command register, and
a static random access memory,
wherein the controller controls the flash memory and the DRAM to transfer data from the flash memory to the DRAM when an instruction is written into the command register from an outside of the controller.
7. A controller according to claim 6 , further comprising:
a terminal outputting a signal during transferring the data from the flash memory to the DRAM.
8. A controller according to claim 6 ,
wherein the flash memory is a NAND type flash memory,
wherein the DRAM is a DDR-SDARM, and
wherein the controller further includes:
a clock input terminal receiving a first clock signal, and
a clock output terminal providing a second clock signal based on the first clock signal to the DDR-SDRAM.
9. A controller according to claim 6 ,
wherein the instruction is a load instruction.
10. A controller for use with a NAND type flash memory and a DDR-SDRAM, the controller comprising:
a command register,
a clock input terminal receiving a first clock signal, and
a clock output terminal providing a second clock signal based on the first clock signal to the DDR-SDRAM,
the controller controlling the NAND type flash memory and the DDR-SDRAM to transfer data from the NAND type flash memory to the DDR-SDRAM when an instruction is supplied to the command register from an outside of the controller.
11. A controller according to claim 10 ,
wherein the instruction is a load instruction.
12. A controller according to claim 10 , further comprising:
a terminal outputting a signal during transferring the data from the NAND type flash memory to the DDR-SDRAM.
13. A controller for use with a NAND type flash memory and a SDRAM, the controller comprising:
a command register, and
an error correction circuit detecting whether or not data read out from the NAND type flash memory includes an error therein and correcting the error thereof when checking,
the controller controlling the NAND type flash memory and the SDRAM to transfer the data from the NAND type flash memory to the SDRAM when an instruction is supplied to the command register from an outside of the memory module.
14. A controller according to claim 13 , further comprising:
a terminal outputting a signal during transferring the data from the NAND type flash memory to the SDRAM.
15. A controller according to claim 13 , wherein the instruction is a load instruction.
16. A controller according to claim 13 , wherein the controller further includes:
a clock input terminal receiving a first clock signal, and
a clock output terminal providing a second clock signal based on the first clock signal to the SDRAM.
17. A controller for use with a NAND type flash memory and a DRAM synchronized with a clock, the controller comprising:
a command register,
the controller controlling the NAND type flash memory and the DRAM to transfer data from the NAND type flash memory to the DRAM when a first instruction code is written into the command register from an outside of the memory module and controlling the NAND type flash memory and the DRAM to transfer data from the DRAM to the NAND type flash memory to transfer data from the DRAM to the NAND type memory when a second instruction code is written into the command register from the outside of the memory module.
18. A controller according to claim 17 , further comprising:
a terminal outputting a signal during transferring the data from the NAND type flash memory to the DRAM or during transferring the data from the DRAM to the NAND type flash memory.
19. A controller according to claim 17 ,
wherein the first instruction code is a load instruction code, and
wherein the second instruction code is a store command.
20. A controller according to claim 17 , further includes:
an error correction circuit to detect whether or not the data read from the NAND type flash memory contains an error and to correct the error when detected.
21. A controller according to claim 17 , further includes:
a clock input terminal receiving a first clock signal, and
a clock output terminal providing a second clock signal based on the first clock signal to the DRAM.
22. A controller according to claim 21 ,
wherein the DRAM is a DDR-SDRAM.
23. A controller according to claim 21 , further including:
a SRAM.