Method of fabricating semiconductor device
View Patent ↗There is provided a method of fabricating a semiconductor including: forming a first and a second bipolar transistors on a semiconductor substrate; forming a dummy layer on, or on the periphery of, at least one region of the emitter region, the base region, or the collector region of the second bipolar transistor and on an area surrounding a contact region for establishing an electrical connection to the outside in the at least one of the emitter region, the base region, or the collector region; forming an insulation layer so as to cover the first bipolar transistor, the second bipolar transistor, and the dummy layer; forming, together with the insulation layer and in a contact region of each region of the first bipolar transistor and the second bipolar transistor, a contact hole for establishing contact with each of those regions; and embedding a conductive member in the contact holes.
1. A method of fabricating a semiconductor, the method comprising:
forming a first bipolar transistor including an emitter region, a base region, and a collector region on a semiconductor substrate;
forming a second bipolar transistor including an emitter region, a base region, and a collector region on the semiconductor substrate;
forming a dummy layer on, or on the periphery of, at least one region of the emitter region, the base region, or the collector region of the second bipolar transistor and on an area surrounding a contact region configured to establish an electrical connection to the outside in the at least one of the emitter region, the base region, or the collector region;
forming an insulation layer so as to cover the first bipolar transistor, the second bipolar transistor, and the dummy layer;
forming, together with the insulation layer and in a contact region of each region of the first bipolar transistor and the second bipolar transistor, contact holes for establishing contact with each of those regions, the contact holes including contact holes to the emitter region, the collector region, and the base region, respectively; and
embedding a conductive member in the contact holes;
wherein at least one of the contact holes to the at least one region of the emitter region, the base region, or the collector region of the second bipolar transistor, on which the dummy layer is formed, is formed with a shallower contact depth than the contact hole of at least one region of the emitter region, the base region, or the collector region of the first bipolar transistor.
2. The method according to claim 1 , wherein in the forming of the dummy layer, the dummy layer is formed surrounding or sandwiching the contact region in the at least one of the emitter region, the base region, or the collector region.
3. The method according to claim 1 , wherein in the forming of the dummy layer, the dummy layer is formed unevenly distributed on one side of the contact region in the at least one of the emitter region, the base region, or the collector region.
4. The method according to claim 1 , wherein the dummy layer is a polysilicon layer.
5. The method according to claim 4 , wherein in the forming of the dummy layer, the dummy layer is formed so as to contact the conductive member embedded in the contact hole.
6. The method according to claim 4 , further comprising forming a MOS transistor on the semiconductor substrate, wherein in the forming of the dummy layer, the polysilicon layer that becomes the dummy layer and a polysilicon layer that becomes a gate electrode of the MOS transistor are formed at the same time.
7. The method according to claim 6 , wherein the MOS transistor is at least one selected from a CMOS transistor or a DMOS transistor.
8. The method according to claim 1 , wherein in the forming of the dummy layer, the dummy layer is formed on, or on the periphery of, the emitter region of the second bipolar transistor and on the environs of the contact region in that emitter region.
9. The method according to claim 1 , wherein in the forming of the contact holes, the diameters of each of the contact holes formed in the contact regions of each region of the first bipolar transistor and the second bipolar transistor are a single size.
10. A method of fabricating a semiconductor, the method comprising:
forming a first bipolar transistor including an emitter region, a base region, and a collector region on a semiconductor substrate;
forming a second bipolar transistor including an emitter region, a base region, and a collector region on the semiconductor substrate;
forming a dummy layer on, or on the periphery of, at least one region of the emitter region, the base region, or the collector region of the second bipolar transistor and on an area surrounding a contact region configured to establish an electrical connection to the outside in the at least one of the emitter region, the base region, or the collector region;
forming an insulation layer so as to cover the first bipolar transistor, the second bipolar transistor, and the dummy layer;
forming, together with the insulation layer and in a contact region of each region of the first bipolar transistor and the second bipolar transistor, contact holes for establishing contact with each of those regions, the contact holes including a contact hole to the emitter region; and
embedding a conductive member in the contact holes;
wherein the contact hole in the emitter region of the second bipolar transistor, on which the dummy layer is formed, is formed with a shallower contact depth than the contact hole in the emitter region of the first bipolar transistor.
11. The method according to claim 10 , wherein a bottom surface of the contact hole formed in the contact region of the emitter region of the second bipolar transistor is formed slanting with respect to a surface of the semiconductor substrate.