Radiation hard and fault tolerant multicore processor and method for ionizing radiation environment
A redundancy system in a fault tolerant computer comprises a multiple core processor which may support a real time operating system. The multiple core machine may be actual or virtual. Multiple identical instructions, e.g., three instructions, are executed redundantly so that the redundancy system can detect and recover from a single event upset (SEU). The instructions are also displaced in time. In one form, two non-consecutive instructions are run on one core which is virtualized into two cores. Alternatively, a second actual core may provide symmetric processing. The system prevents single event functional interrupts (SEFIs) from hanging up the processor. Each core may run a separate operating system. When a first core hangs up a first operating system, the second operating system takes over operation and the processor recovers. Embedded routines may store selected data variables in memory for later recovery and perform an SEFI “self-test” routine.
1. A redundancy system in a fault tolerant computer comprising: a processor having at least two cores to execute instructions, at least two operating systems each running on one of said at least two cores and each providing a separate software thread, said processor including instructions to execute first and second identical instructions to the processor to produce first and second respective results to be compared in a redundancy routine, said compared results being produced during separate time periods, a comparison command executed in one of said cores, said comparison providing an output indicative of equality or inequality of said first and second results, an indication of inequality comprising an SEU error signal, and producing a third instruction signal coupled for voting in one of said cores in response to an SEU error signal, said processor having a real time operating system and a processing rate of at least one gigahertz.
2. The redundancy system according to claim 1 wherein said processor comprises a multicore virtual machine.
3. A redundancy system in a fault tolerant computer comprising: a processor having at least two cores to execute instructions, at least two operating systems each running on one of said at least two cores and each providing a separate software thread, said processor including instructions to execute first and second identical instructions to the processor to produce first and second respective results to be compared in a redundancy routine, said compared results being produced during separate time periods, a comparison circuit coupled to compare said first and second results, said comparison circuit providing an output indicative of equality or inequality of said first and second results, an indication of inequality comprising an SEU error signal, and producing a third instruction signal coupled for voting in response to an SEU error signal, said processor having a real time operating system and a processing rate of at least one gigahertz, wherein said processor comprises a multicore virtual machine, and wherein said multicore virtual machine comprises a single core and a virtualizing circuit resolving said core into first and second virtual circuit boards, and a timing circuit for processing the first instruction on the first virtual circuit board, processing the second instruction on the second virtual circuit board, and for processing the third instruction on the first virtual circuit board at a later time.
4. The redundancy system according to claim 3 wherein said multicore virtual machine comprises a first core and a second core and a virtualizing circuit resolving said first core into first and second virtual circuit boards.
5. The redundancy system according to claim 4 further comprising a second virtualizing circuit connected for providing at least one virtual circuit board on the second core.
6. The redundancy system according to claim 5 wherein each said core runs separate copies of the same operating system.
7. The redundancy system according to claim 5 wherein at least two cores each run a different operating system.
8. A redundancy system in a fault tolerant computer also including an SEFI detection and recovery circuit comprising: a multiple core processor having a first and a second real time operating system, each operating system running on a separate core, a redundancy circuit to detect and recover from a single event upset, the redundancy circuit being coupled to compare first and second results each produced in a separate time period, the comparison being executed in one of said cores, and further comprising a hang detecting circuit responsive to failure to receive a signal indicative of operation of one operating system of said processor, said hang detector circuit responding to absence of a processor output at a predetermined count of a first program counter, said hang detector being further coupled to respond to a second program counter providing a program count for detecting hang of said second operating system, and means responsive to said hang detector to switch operation to said first or second operating system which is not hung.
9. An SEFI detection and recovery circuit comprising: a multiple core processor having a first and a second real time operating system, each operating system running on a separate core, a redundancy circuit being coupled to compare first and second results each produced in a separate time period, the comparison being executed in one of said cores, a hang detecting circuit responsive to failure to receive a signal indicative of operation of one operating system of said processor, said hang detector circuit responding to absence of a processor output at a predetermined count of a first program counter, said hang detector being further coupled to respond to a second program counter providing a program count for detecting hang of said second operating system, and means responsive to said hang detector to switch operation to said first or second operating system which is not hung.
10. The SEFI detection and recovery circuit according to claim 9 wherein said first and second operating systems comprise copies of the same operating system program.
11. A redundancy system in a fault tolerant computer comprising: a processor having at least two cores to execute instructions, at least a first operating system and a second operating system each running on a separate one of said at least two cores and providing a software thread, said processor including instructions to execute first and second identical instructions to the processor to produce first and second respective results to be compared in a redundancy routine, said compared results being produced during separate time periods, said comparison being performed in one of said cores, a comparison command executed in one of said cores, said comparison providing an output indicative of equality or inequality of said first and second results, an indication of inequality comprising an SEU error signal, and producing a third instruction signal coupled for voting in one of said cores in response to an SEU error signal, said processor having a real time operating system and a processing rate of at least one gigahertz.
12. The redundancy system according to claim 11 wherein said processor comprises a multicore virtual machine.
13. The redundancy system according to claim 12 wherein said multicore virtual machine comprises a single core and a virtualizing circuit resolving said core into first and second virtual circuit boards, and a timing circuit for processing the first instruction on the first virtual circuit board, processing the second instruction on the second virtual circuit board, and for processing the third instruction on the first virtual circuit board at a later time.
14. A redundancy system in a fault tolerant computer comprising: a processor having at least two cores to execute instructions and a first operating system and a second operating system running on a first core and a second core of said at least two cores respectively, said processor including instructions to execute first and second identical instructions to the processor to produce first and second respective results to be compared in a redundancy routine, said compared results being produced during separate time periods, a comparison command executed in one of said cores, said comparison providing an output indicative of equality or inequality of said first and second results, an indication of inequality comprising an SEU error signal, and producing a third instruction signal coupled for voting in one of said cores in response to an SEU error signal, said processor having a real time operating system and a processing rate of at least one gigahertz.
15. The redundancy system according to claim 14 wherein said processor comprises a multicore virtual machine.
16. The redundancy system according to claim 15 wherein said multicore virtual machine comprises a single core and a virtualizing circuit resolving said core into first and second virtual circuit boards, and a timing circuit for processing the first instruction on the first virtual circuit board, processing the second instruction on the second virtual circuit board, and for processing the third instruction on the first virtual circuit board at a later time.