Semiconductor storage device
A device includes a memory cell array having a plurality of memory cells; sense amplifiers, which are arranged adjacent to the memory cell array, for amplifying signals that have been read out of corresponding ones of the memory cells; readout signal lines; a plurality of connection circuits for selectively connecting the sense amplifiers and the readout signal lines; a plurality of main amplifiers for amplifying and outputting signals that have been read out of the sense amplifiers via the readout signal lines by the connection circuits selected by selection signals; an enable signal line connected to the main amplifiers; and an enable signal generating circuit for outputting a main amplifier enable signal to the enable signal line. The enable signal generating circuit is placed in close proximity to the connection circuits.
1 . A semiconductor storage device, comprising:
a memory cell array having a plurality of memory cells;
sense amplifiers, which are arranged adjacent to said memory cell array, for amplifying signals that have been read out of corresponding ones of the memory cells;
readout signal lines;
a plurality of connection circuits for selectively connecting said sense amplifiers and said readout signal lines;
a plurality of main amplifiers for amplifying and outputting signals that have been read out of said sense amplifiers via said readout signal lines by said connection circuits selected by selection signals;
an enable signal line connected to said main amplifiers; and
an enable signal generating circuit for outputting a main amplifier enable signal to said enable signal line;
wherein said enable signal generating circuit is placed in close proximity to the connection circuits.
2 . The device according to claim 1 , wherein said enable signal generating circuit responds to receipt of the selection signal by generating the enable signal in conformity with timing at which said sense amplifiers and said readout signal lines are connected by said connection circuits.
3 . The device according to claim 2 , wherein said enable signal line is routed in close proximity to said readout signal lines.
4 . The device according to claim 1 , wherein said connection circuits connect a plurality of said sense amplifiers and a corresponding plurality or plurality of sets of said readout signal lines.
5 . The device according to claim 4 , wherein said enable signal generating circuit is connected to each of said plurality of connection circuits via said enable signal line and the enable signal causes said plurality of main amplifiers to start simultaneously.
6 . A semiconductor storage device, comprising:
a memory cell array having a plurality of memory cells;
sense amplifiers, which are arranged adjacent to said memory cell array, for amplifying signals that have been read out of corresponding ones of the memory cells;
readout signal lines;
connection circuits for selectively connecting said sense amplifiers and said readout signal lines;
a plurality of main amplifiers for amplifying and outputting signals that have been read out of said sense amplifiers via said readout signal lines by said connection circuits selected by selection signals;
a reference signal line connected to said main amplifiers; and
a reference signal generating circuit for outputting a main amplifier reference signal to said reference signal line;
wherein aid reference signal generating circuit is placed in close proximity to said connection circuits.
7 . The device according to claim 6 , wherein said reference signal generating circuit responds to receipt of the selection signal by generating the reference signal in conformity with timing at which the sense amplifiers and the readout signal lines are connected by said connection circuits.
8 . The device according to claim 7 , wherein said reference signal line is routed in close proximity to said readout signal lines.
9 . The device according to claim 7 , wherein said connection circuits connect a plurality of said sense amplifiers and a corresponding plurality of said readout signal lines.
10 . The device according to claim 7 , wherein said reference signal generating circuit is connected to each of said plurality of main amplifiers via said reference signal line, and the reference signal is shared by said plurality of main amplifiers.