Thin film transistor, fabrication method of same, and display device having the same

1. A method for manufacturing a thin film transistor including a semiconductor layer made of polysilicon, the method comprising:

forming a metal pattern on a substrate;

forming a first insulating layer on the metal pattern;

forming an amorphous silicon layer on the first insulating layer;

crystallizing the amorphous silicon layer into a polysilicon layer by using a directional lateral solidification process; and

patterning the polysilicon layer to form the semiconductor layer,

wherein the directional lateral solidification process includes a repetitive crystallization process including:

performing a first irradiation to one predetermined region of the amorphous silicon layer with a line-shaped laser beam having a predetermined length, width and energy density to completely melt amorphous silicon in the one predetermined region, thereby providing melted silicon in the one predetermined region,

allowing the melted silicon in the one predetermined region of the amorphous silicon layer to cool and crystallize into polysilicon,

moving the laser beam by less than half of the width of the laser beam in a first direction to another predetermined region, such that the other predetermined region includes a portion of the polysilicon crystallized in the one predetermined region, and

performing a secondary irradiation to the other predetermined region to completely melt the polysilicon and amorphous silicon in the other predetermined region, thereby providing melted silicon in the other predetermined region.

2. The method as claimed in claim 1 , wherein the line-shaped laser beam is a pulse-type laser beam and has a length of about 365 nm to about 1100 nm, a width of about 5 to about 20 μm, and an energy density of about 150 to about 1000 mJ/cm 2 .

3. The method as claimed in claim 2 , wherein:

the polysilicon layer includes a grain boundary parallel to the first direction, and

the polysilicon layer is crystallized to have a surface roughness defined by a distance between a lowest peak and a highest peak in a surface thereof of less than about 15 nm.

4. The method as claimed in claim 3 , wherein the grain boundary is parallel to a current flow direction.

5. The method as claimed in claim 1 , wherein:

the metal pattern is a gate electrode corresponding to a portion of the semiconductor layer, and

the first insulating layer is a gate insulating layer.

6. The method as claimed in claim 5 , further comprising:

forming an interlayer insulating layer on the semiconductor layer; and

forming a source/drain electrode on the interlayer insulating layer such that the source/drain electrode is electrically connected to one side of the semiconductor layer.

7. The method as claimed in claim 1 , wherein the metal pattern is a light blocking member including one or a plurality of opaque layers.

8. The method as claimed in claim 7 , wherein the opaque layer includes carbon or at least one of Fe, Co, V, Ti, Al, Ag, Si, Ge, Y, Zn, Zr, W, Ta, Cu, and Pt.

9. The method as claimed in claim 7 , further comprising:

forming a gate insulating layer on the semiconductor layer;

forming a gate electrode on the gate insulating layer such that the gate electrode overlaps a portion of the semiconductor layer;

forming an interlayer insulating layer on the gate electrode; and

forming a source/drain electrode on the interlayer insulating layer such that the source/drain electrode is electrically connected to one side of the semiconductor layer.

10. The method as claimed in claim 7 , wherein the metal pattern further includes one or a plurality of transparent layers positioned at a side of or between the one or the plurality of opaque layers.

11. The method as claimed in claim 10 , wherein the transparent layer includes:

at least one of SiO x (x=1), SiN x (x=1), MgF 2 , CaF 2 , Al 2 O 3 , and SnO 2 , or at least one of ITO, IZO, ZnO, and In 2 O 3 .