System for reducing power consumption and increasing speed of content-addressable memory
View Patent ↗A content addressable memory (CAM) system configured for reduced power consumption and increased speed includes a plurality of bit cells implementing a stacked architecture. Each bit cell comprises a pair of stacked storage elements in a first column and a compare circuit, coupled to the pair of stacked storage elements and a matchline of the CAM system, situated in a second column. The stacked architecture results in a reduced matchline length, thereby reducing CAM system power consumption and increasing CAM system speed. In a further embodiment, a content addressable memory (CAM) system configured for reduced power consumption and increased speed includes storing encoded data in a pair of stacked storage elements.
1. A content-addressable memory (CAM) system configured for reduced power consumption and increased speed, said CAM system comprising:
a plurality of bit cells in a stacked architecture, each of said plurality of bit cells including:
a pair of stacked storage elements situated in a first column substantially perpendicular to a matchline of said CAM system;
a compare circuit coupled to said pair of stacked storage elements and said matchline, said compare circuit situated in a second column;
said stacked architecture reducing a length of said matchline, thereby reducing CAM system power consumption and increasing CAM system speed.
2. The CAM system of claim 1 , wherein said first column adjoins said second column.
3. The CAM system of claim 1 , wherein said pair of stacked storage elements share bit lines.
4. The CAM system of claim 1 , wherein said pair of stacked storage elements are coupled to separate pairs of bit lines.
5. The CAM system of claim 1 , wherein said compare circuit is implemented using a plurality of transistors of the same conductivity type.
6. The CAM system of claim 1 , wherein said compare circuit is further configured to couple to compare lines of said CAM system through compare circuit transistors.
7. The CAM system of claim 1 , wherein said compare circuit comprises a plurality of transistors arranged in pulldown-stack configurations coupled to said matchline.
8. The CAM system of claim 1 , wherein said compare circuit comprises a plurality of transistors arranged in one pulldown-stack configuration coupled to said matchline.
9. The CAM system of claim 1 , wherein said compare circuit is further configured to compare data stored in one of said pair of stacked storage elements against compare-data supplied by compare lines of said CAM system and then apply a match or mismatch state to said matchline.
10. The CAM system of claim 1 , wherein said compare circuit is further configured to compare compare-data supplied by compare lines of said CAM system against data stored in said pair of stacked storage elements while concurrently applying a match or mismatch state to said matchline.
11. A content-addressable memory (CAM) bit cell implementing a stacked architecture and comprising:
a pair of stacked storage elements situated in a first column substantially perpendicular to a matchline of said CAM system;
a compare circuit coupled to said pair of stacked storage elements and configured to couple to said matchline, said compare circuit situated in a second column;
said stacked architecture configured to reduce a length of said matchline, thereby reducing CAM system power consumption and increasing CAM system speed.
12. The CAM bit cell of claim 11 , wherein said first column adjoins said second column.
13. The CAM bit cell of claim 11 , wherein said pair of stacked storage elements share bit lines.
14. The CAM bit cell of claim 11 , wherein said pair of stacked storage elements are coupled to separate pairs of bit lines.
15. The CAM bit cell of claim 11 , wherein said compare circuit is implemented using a plurality of transistors of the same conductivity type.
16. The CAM bit cell of claim 11 , wherein said compare circuit is further configured to couple to compare lines of said CAM system through compare circuit transistors.
17. The CAM bit cell of claim 11 , wherein said compare circuit comprises a plurality of transistors arranged in pulldown-stack configurations coupled to said matchline.
18. The CAM bit cell of claim 11 , wherein said compare circuit comprises a plurality of transistors arranged in one pulldown-stack configuration coupled to said matchline.
19. The CAM bit cell of claim 11 , wherein said compare circuit is further configured to compare data stored in one of said pair of stacked storage elements against compare-data supplied by compare lines of said CAM system and then apply a match or mismatch state to said matchline.
20. The CAM bit cell of claim 11 , wherein said compare circuit is further configured to compare compare-data supplied by compare lines of said CAM system against data stored in said pair of stacked storage elements while concurrently applying a match or mismatch state to said matchline.