System and method for dynamically adjusting memory performance
According to an exemplary embodiment, a method for dynamically adjusting memory performance includes detecting a bandwidth of a data transfer. Detecting the bandwidth can comprise measuring a data stream of the data transfer and determining the bandwidth based on the measuring. The method further includes selecting a subset of a plurality of interleaved memory units based on the bandwidth. A device performing the data transfer can comprise a power supply and the selecting can be based on a power level of the power supply. The selecting can also be based on a temperature of the device performing the data transfer. The method also includes performing a data access for the data transfer using the subset of the plurality of interleaved memory units.
1 . A method for dynamically adjusting memory performance, said method comprising:
detecting a bandwidth of a data transfer;
selecting a subset of a plurality of interleaved memory units based on said bandwidth;
performing a data access for said data transfer using said subset of said plurality of interleaved memory units.
2 . The method of claim 1 , wherein said detecting said bandwidth comprises measuring a data stream of said data transfer.
3 . The method of claim 2 , wherein said detecting said bandwidth comprises determining said bandwidth based on said measuring.
4 . The method of claim 1 , wherein said detecting said bandwidth comprises extracting said bandwidth as a data tag from a data stream.
5 . The method of claim 1 , wherein said detecting said bandwidth comprises executing machine code.
6 . The method of claim 1 , wherein a device performing said data transfer comprises a power supply, and wherein said selecting is based on a power level of said power supply.
7 . The method of claim 1 , wherein said selecting is based on a temperature of a device performing said data transfer.
8 . The method of claim 1 , wherein said subset of said plurality of interleaved memory units is a minimum subset of said plurality of interleaved memory units that can support said bandwidth.
9 . The method of claim 1 , wherein said plurality of interleaved memory units comprise flash memory units.
10 . The method of claim 1 , wherein said plurality of interleaved memory units comprise NAND flash memory units.
11 . A system for dynamically adjusting memory performance, said system comprising:
a bandwidth detector configured to detect a bandwidth of a data transfer;
a processor configured to select a subset of a plurality of interleaved memory units based on said bandwidth;
a memory controller configured to perform a data access for said data transfer using said subset of said plurality of interleaved memory units.
12 . The data transfer system of claim 11 , wherein said bandwidth detector comprises a bandwidth detector, said bandwidth detector performing a measurement of a data stream of said data transfer.
13 . The data transfer system of claim 12 , wherein said bandwidth detector determines said bandwidth based on said measurement.
14 . The data transfer system of claim 11 , wherein said bandwidth detector detects said bandwidth by extracting a data tag from a data stream.
15 . The data transfer system of claim 11 , wherein said bandwidth detector comprises executable machine code.
16 . The data transfer system of claim 11 , wherein data transfer system comprises a power supply, and wherein said processor selects said subset of said plurality of interleaved memory units based on a power level of said power supply.
17 . The data transfer system of claim 11 , wherein said processor selects said subset of said plurality of interleaved memory units based on a temperature of said data transfer system.
18 . The data transfer system of claim 11 , wherein said subset of said plurality of interleaved memory units is a minimum subset of said plurality of interleaved memory units that can support said bandwidth.
19 . The data transfer system of claim 11 , wherein said plurality of interleaved memory units comprise flash memory units.
20 . The data transfer system of claim 11 , wherein said plurality of interleaved memory units comprise NAND flash memory units.