Apparatus and method for decoding signals
New capabilities will allow conventional broadcast transmission to be available to mobile devices. A method of decoding a bitstream is described including receiving a demodulated bitstream, the demodulated bitstream encoded using a byte-code encoding process, arranging a portion of the demodulated bitstream into a subset of bits, reordering the subset of bits, and decoding the subset of bits based on a property of the subset of bits and the encoding process. An apparatus includes means for decoding a bitstream based on a property of the subset of bits and the encoding process.
1. A method of decoding a bitstream, comprising:
receiving a demodulated bitstream, the demodulated bitstream encoded using a byte-code encoding process;
arranging the demodulated bitstream into a plurality of subsets, each subset containing a plurality of bits;
identifying a set of symbols in each of the subsets, each symbol including at least two bits in the subset, the set of symbols related to a modulation format for the demodulated bitstream;
reordering the set of symbols in each subset of the plurality of subsets; and
decoding each reordered subset based on a trellis relationship between the set of symbols in the reordered subset and a parity checking relationship between the bits in the reordered subset.
2. The method of claim 1 , wherein the parity checking relationship is a set of parity check relationships.
3. The method of claim 2 , wherein the set of parity check relationships are parity equations.
4. The method of claim 1 , wherein the decoding includes a convolutional decoding process.
5. The method of claim 1 , wherein the byte-code encoding process is based on a short linear block code in the Galois Field 256 space.
6. An apparatus for decoding a bitstream, comprising:
means for receiving a demodulated bitstream, the demodulated bitstream encoded using a byte-code encoding process;
means for arranging the demodulated bitstream into a plurality of subsets, each subset containing a plurality of bits;
means for identifying a set of symbols in each of the subsets, each symbol including at least two bits in the subset, the set of symbols related to a modulation format for the demodulated bitstream;
means for reordering the set of symbols in each subset of the plurality of subsets; and
means for decoding each reordered subset based on a trellis relationship between the set of symbols in the reordered subset and a parity checking relationship between the bits in the reordered subset.
7. The apparatus of claim 6 , wherein the parity checking relationship is a set of parity checking relationships.
8. The apparatus of claim 7 , wherein the set of parity checking relationships are parity equations.
9. The apparatus of claim 6 , wherein the means for decoding includes a convolutional decoding process.
10. The apparatus of claim 6 , wherein the byte-code encoding process is based on a short linear block code in the Galois Field 256 space.
11. An apparatus for decoding a bitstream, comprising:
an input controller that receives a demodulated bitstream, the demodulated bitstream encoded using a byte-code encoding process;
an input re-ordering device that arranges the demodulated bitstream into a plurality of subsets, each subset containing a plurality of bits, the input re-ordering device identifies a set of symbols in each of the subsets, each symbol including at least two bits in the subset, the set of symbols related to a modulation format for the demodulated bitstream, the input re-ordering device further reorders the set of symbols in each subset of the plurality of subsets; and
at least one trellis decoder that decodes each reordered subset based on a trellis relationship between the set of symbols in the reordered subset and a parity checking relationship between the bits in the reordered subset.
12. The apparatus of claim 11 , wherein the parity checking relationship is a set of parity checking relationships.
13. The apparatus of claim 12 , wherein the set of parity checking relationships are parity equations.
14. The apparatus of claim 11 , wherein the at least one trellis decoder includes a convolutional decoding process.
15. The apparatus of claim 11 , wherein the byte-code encoding process is based on a short linear block code in the Galois Field 256 space.