Phase-locked loop modulation
View Patent ↗A phase-locked loop having: an oscillator for forming an oscillating output signal; a frequency divider connected to receive the output of the oscillator and frequency divide it by a value dependent on a division control signal; and a phase comparator for comparing the phase of the divided signal and a reference signal to generate a control signal, the operation of the oscillator being dependent on the control signal; the output data to form a divided signal a division ratio controller configured to, when clocked by an input signal, generate a series of output data for forming the division control signal; the phase-locked loop having: a first mode of operation in which the frequency divider is operable to frequency divide the output of the oscillator by a value dependent on the output of the division ratio controller; and a second mode of operation in which the frequency divider is not operable to frequency divide the output of the oscillator by a value dependent on the output of the division ratio controller, and the division ratio controller is clocked by a signal that is independent of the output of the oscillator.
1. A phase-locked loop having:
an oscillator for forming an oscillating output signal;
a frequency divider connected to receive the output of the oscillator and frequency divide it by a value dependent on a division control signal;
a phase comparator for comparing the phase of the divided signal and a reference signal to generate a control signal, the operation of the oscillator being dependent on the control signal;
a first sigma-delta modulator configured to, when clocked by an input signal, generate a series of output data for forming the division control signal;
a second sigma-delta modulator configured to, when clocked by an input signal, generate a series of output data for forming the division control signal;
the phase-locked loop having:
a first mode of operation in which the frequency divider is operable to frequency divide the output of the oscillator by a value dependent on the output data of the first sigma-delta modulator; and
a second mode of operation in which the frequency divider is operable to frequency divide the output of the oscillator by a value not dependent on the output data of the first sigma-delta modulator, but by a value dependent on the output data of the second sigma-delta modulator, wherein the input signals by which the first and second sigma-delta modulators are clocked are independent of the output of the oscillator.
2. The phase-locked loop as claimed in claim 1 , wherein the phase-locked loop is capable of switching from the first mode of operation to the second mode of operation and is configured so that whilst the phase-locked loop is operating in the second mode following such switching the first sigma-delta modulator maintains its state as if the phase-locked loop were operating in the first mode.
3. The phase-locked loop as claimed in claim 1 , wherein the frequency divider is operable to frequency divide the output of the oscillator by the output of the first sigma-delta modulator.
4. The phase-locked loop as claimed in claim 1 , wherein the frequency divider is operable to frequency divide the output of the oscillator by the output of the first sigma-delta modulator plus a predetermined constant.
5. The phase-locked loop as claimed in claim 1 , wherein the first sigma-delta modulator is configured to output only integers.
6. The phase-locked loop as claimed in claim 1 , wherein the first sigma-delta modulator is configured to output only values from a set whose members that differ by two or less.
7. The phase-locked loop as claimed in claim 4 , wherein the first sigma-delta modulator is configured to output only the values −1, 0 and +1.
8. The phase-locked loop as claimed in claim 1 , wherein the first sigma-delta modulator is configured to output values in Gray coded form.
9. The phase-locked loop as claimed in claim 1 , comprising a sample-and-hold circuit arranged to store the most recent output of the first sigma-delta modulator, the frequency divider being configured to frequency divide the output of the oscillator by the value stored by the sample-and-hold circuit.
10. The phase-locked loop as claimed in claim 1 , wherein the phase-locked loop is a fractional N phase-locked loop.
11. A signal receiver comprising:
the phase-locked loop as claimed in claim 1 ; and
a downconverter for downconverting a received signal in dependence on the output of the oscillator.
12. The signal receiver as claimed in claim 11 , wherein the downconverter comprises a mixer configured to mix a received signal with a signal whose frequency is dependent on the output of the oscillator.
13. The signal receiver as claimed in claim 11 , the receiver having a first mode for receiving signals of a first protocol and a second mode for receiving signals of a second protocol, and being arranged to control the phase-locked loop to operate in its first mode when the receiver is operating in its first mode and to control the phase-locked loop to operate in its second mode when the receiver is operating in its second mode.
14. A signal transmitter comprising:
the phase-locked loop as claimed in claim 1 ; and
an upconverter for upconverting a signal for transmission in dependence on the output of the oscillator.
15. The signal transmitter as claimed in claim 14 , wherein the upconverter comprises a mixer configured to mix a signal for transmission with a signal whose frequency is dependent on the output of the oscillator.
16. The signal transmitter as claimed in claim 14 , the transmitter having a first mode for transmitting signals of a first protocol and a second mode for transmitting signals of a second protocol, and being arranged to control the phase-locked loop to operate in its first mode when the transmitter is operating in its first mode and to control the phase-locked loop to operate in its second mode when the transmitter is operating in its second mode.