IP Library Granted Patent US 8,318,594
Granted Patent B2
US 8,318,594 · App. 12/937,756 · Granted Nov 27, 2012

Method for fabricating nitride-based semiconductor device having electrode on m-plane

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,318,594
App. No.
12/937,756
Granted
Nov 27, 2012
Kind
B2
Abstract

A nitride-based semiconductor light-emitting device 100 includes: a GaN substrate 10 with an m-plane surface 12 ; a semiconductor multilayer structure 20 provided on the m-plane surface 12 of the GaN substrate 10 ; and an electrode 30 provided on the semiconductor multilayer structure 20 . The electrode 30 includes an Mg layer 32 and an Ag layer 34 provided on the Mg layer 32 . The Mg layer 32 is in contact with a surface of a p-type semiconductor region of the semiconductor multilayer structure 20.

Claims (16)

1. A method for fabricating a nitride-based semiconductor device, comprising the steps of:

(a) providing a substrate;

(b) forming on the substrate a nitride-based semiconductor multilayer structure including a p-type GaN-based semiconductor region, a surface of the p-type GaN-based semiconductor region being an m-plane; and

(c) forming an electrode on the surface of the p-type GaN-based semiconductor region of the semiconductor multilayer structure,

wherein step (c) includes

forming a Mg layer on the surface of the p-type GaN-based semiconductor region, and

forming a Ag layer on the Mg layer, and

performing a heat treatment to anneal the electrode at a temperature of 500° C. to 700° C., and

wherein a contact resistance of the electrode arranged on the m-plane and annealed at a temperature of 500° C. to 700° C. is less than 1.0×10 −02 Ωcm 2 , and is lower than a contact resistance when the electrode is arranged on a c-plane of the same p-type semiconductor region and annealed at a temperature of 500° C. to 700° C.

2. The method of claim 1 , wherein the heat treatment is performed at a temperature of 550° C. to 600° C.

3. The method of claim 1 , wherein the p-type GaN-based semiconductor region is made of an Al x In y Ga z N semiconductor (where x+y+z=1, x≧0, y≧0, and z>0).

4. The method of claim 3 , wherein the step of forming the Mg layer includes irradiating Mg with pulses of an electron beam such that Mg is deposited onto the surface of the p-type GaN-based semiconductor region.

5. The method of claim 3 , further comprising removing the substrate after step (b).

6. The method of claim 3 , wherein the p-type GaN-based semiconductor region is made of GaN.

7. The method of claim 1 , wherein a Mg—Ag alloy layer is formed between the Mg layer and the Ag layer after the heat treatment.

8. The method of claim 1 , wherein the Ag layer is provided directly on the Mg layer.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERRONEOUSLY FILED APPLICATION NUMBERS 13/384239, 13/498734, 14/116681 AND 14/301144 PREVIOUSLY RECORDED ON REEL 034194 FRAME 0143. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Dec 24, 2020
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 056788/0362 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2014
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 034194/0143 →