Method for designing a semiconductor device including stress films
A method for designing a semiconductor device includes arranging at least a pattern of a first active region in which a first transistor is formed and a pattern of a second active region in which a second transistor is formed; arranging at least a pattern of a gate wire which intersects the first active region and the second active region; extracting at least a first region in which the first active region and the gate wire are overlapped with each other; arranging at least one pattern of a compressive stress film on a region including the first active region; and obtaining by a computer a layout pattern of the semiconductor device, when the at least one pattern of the compressive stress film is arranged, end portions of the at least one pattern thereof are positioned based on positions of end portions of the first region.
1. A method for designing a semiconductor device comprising:
arranging at least a pattern of a first active region in which a first transistor is formed and a pattern of a second active region in which a second transistor is formed;
arranging at least a pattern of a gate wire which intersects the first active region and the second active region;
extracting at least a first region in which the first active region and the gate wire are overlapped with each other;
arranging a pattern of a tensile stress film;
arranging at least one pattern of a compressive stress film on a region including the first active region so as to be surrounded on a region including the second active region by the tensile stress film and have a projective portion at a portion where the at least one compressive stress film is contact with the tensile stress film; and
obtaining by a computer a layout pattern of the semiconductor device, when the at least one pattern of the compressive stress film is arranged, end portions of the at least one pattern thereof are positioned based on positions of end portions of the first region.
2. The method for designing a semiconductor device according to claim 1 , wherein: arranging at least the patterns of the first and second active regions includes arranging patterns of a plurality of the first active regions and patterns of a plurality of the second active regions, arranging at least the pattern of the gate wire includes arranging patterns of a plurality of the gate wires, extracting at least the first region includes extracting a plurality of the first regions, and arranging the at least one pattern of the compressive stress film includes, after the first regions are each extended by a first value in a longitudinal direction of the gate wires and by a second value in a direction perpendicular to the longitudinal direction of the gate wires, merging together the first regions which are partially overlapped with each other by the extensions to obtain a pattern, and producing the at least one pattern of the compressive stress film based on the pattern thus obtained.
3. The method for designing a semiconductor device according to claim 1 , wherein: arranging at least the patterns of the first and second active regions includes arranging patterns of a plurality of the first active regions and patterns of a plurality of the second active regions, arranging at least the pattern of the gate wire includes arranging patterns of a plurality of the gate wires, extracting at least the first region includes extracting a plurality of the first regions, and arranging the at least one pattern of the compressive stress film includes arranging the distances in a longitudinal direction of the gate wires from the end portions of the first regions to the end portions of the at least one pattern of the compressive stress film are set to a first value.
4. The method for designing a semiconductor device according to claim 2 , wherein: arranging at least the patterns of the first and second active regions includes arranging a pattern of one first active region and a pattern of another first active region adjacent to each other in the longitudinal direction of the gate wires so that a space between the pattern of one first active region and the pattern of another first active region is set two or more times the first value, and arranging the at least one pattern of the compressive stress film includes arranging a pattern of one compressive stress film on a region including the one first active region, a pattern of another compressive stress film on a region including the another first active region, and the tensile stress film between the pattern of one compressive stress film and the pattern of another compressive stress film.
5. The method for designing a semiconductor device according to claim 1 , wherein the compressive stress film and the compressive stress film are not overlapped each other at the boundary.
6. The method for designing a semiconductor device according to claim 1 , wherein a thickness of the compressive stress film is thicker than a thickness of the tensile stress film at a boundary between the compressive stress film and the tensile stress film.
7. A method for manufacturing a semiconductor device using a layout pattern comprising:
arranging at least a pattern of a first active region in which a first transistor is formed and a pattern of a second active region in which a second transistor is formed;
arranging at least a pattern of a gate wire which intersects the first active region and the second active region;
extracting at least a first region in which the first active region and the gate wire are overlapped with each other;
arranging a pattern of a tensile stress film;
arranging at least one pattern of a compressive stress film on a region including the first active region so as to be surrounded on a region including the second active region by the tensile stress film and have a projective portion at a portion where the at least one compressive stress film is contact with the tensile stress film; and
obtaining by a computer the layout pattern, when the at least one pattern of the compressive stress film is arranged, end portions of the at least one pattern of the compressive stress film are positioned based on positions of end portions of the first region.
8. The method for manufacturing a semiconductor device according to claim 7 , wherein: arranging at least the patterns of the first and second active regions includes arranging patterns of a plurality of the first active regions and patterns of a plurality of the second active regions, arranging at least the pattern of the gate wire includes arranging patterns of a plurality of the gate wires, extracting at least the first region includes extracting a plurality of the first regions are extracted, and arranging the at least one pattern of the compressive stress film includes, after the first regions are each extended by a first value in a longitudinal direction of the gate wires and by a second value in a direction perpendicular to the longitudinal direction of the gate wires, merging together the first regions which are partially overlapped with each other by the extensions to obtain a pattern, and producing the at least one pattern of the compressive stress film based on the pattern thus obtained.
9. The method for manufacturing a semiconductor device according to claim 8 , wherein: arranging at least the patterns of the first and second active regions includes arranging a pattern of one first active region and a pattern of another first active region adjacent to each other in the longitudinal direction of the gate wires so that a space between the pattern of one first active region and the pattern of another first active region is set two times or more times the first value, and arranging the at least one pattern of the compressive stress film includes arranging a pattern of one compressive stress film on a region including the one first active region, a pattern of another compressive stress film on a region including the another first active region, and the tensile stress film between the pattern of one compressive stress film and the pattern of another compressive stress film.
10. The method for manufacturing a semiconductor device according to claim 7 , wherein: arranging at least the patterns of the first and second active regions includes arranging patterns of a plurality of the first active regions and patterns of a plurality of the second active regions, arranging at least the pattern of the gate wire includes arranging patterns of a plurality of the gate wires, extracting at least the first region includes extracting a plurality of the first regions, and arranging the at least one pattern of the compressive stress film includes arranging the distances in a longitudinal direction of the gate wires from the end portions of the first regions to the end portions of the at least one pattern of the compressive stress film are set to a first value.
11. The method for manufacturing a semiconductor device according to claim 7 , wherein the compressive stress film and the compressive stress film are not overlapped each other at the boundary.
12. The method for manufacturing a semiconductor device according to claim 7 , wherein a thickness of the compressive stress film is thicker than a thickness of the tensile stress film at a boundary between the compressive stress film and the tensile stress film.
13. A method for manufacturing a semiconductor device using a layout pattern comprising:
arranging at least a pattern of a first active region in which a first transistor is formed and a pattern of a second active region in which a second transistor is formed;
arranging at least a pattern of a gate wire which intersects the first active region and the second active region;
extracting at least a first region in which the first active region and the gate wire are overlapped with each other;
arranging at least one pattern of a compressive stress film on a region including the first active region;
arranging a pattern of a tensile stress film adjacent to the compressive stress film on a region including the second active region; and
obtaining by a computer the layout pattern, when the at least one pattern of the compressive stress film is arranged, end portions of the at least one pattern of the compressive stress film are positioned based on positions of end portions of the first region;
wherein:
arranging at least the patterns of the first and second active regions includes arranging patterns of a plurality of the first active regions and patterns of a plurality of the second active regions;
arranging at least the pattern of the gate wire includes arranging patterns of a plurality of the gate wires; extracting at least the first region includes extracting a plurality of the first regions are extracted; and
arranging the at least one pattern of the compressive stress film includes,
after the first regions are each extended by a first value in a longitudinal direction of the gate wires and by a second value in a direction perpendicular to the longitudinal direction of the gate wires, merging together the first regions which are partially overlapped with each other by the extensions to obtain a pattern, and
producing the at least one pattern of the compressive stress film based on the pattern thus obtained;
wherein:
arranging at least the patterns of the first and second active regions includes arranging a pattern of one first active region and a pattern of another first active region adjacent to each other in the longitudinal direction of the gate wires so that a space between the pattern of one first active region and the pattern of another first active region is set two times or more times the first value, and
arranging the at least one pattern of the compressive stress film includes arranging a pattern of one compressive stress film on a region including the one first active region, a pattern of another compressive stress film on a region including the another first active region, and the tensile stress film between the pattern of one compressive stress film and the pattern of another compressive stress film.