IP Library Granted Patent US 9,093,328
Granted Patent B2
US 9,093,328 · App. 12/938,533 · Granted Jul 28, 2015

Semiconductor device having an oxide semiconductor with a crystalline region and manufacturing method thereof

Inventors: Shunpei Yamazaki (Setagaya, JP); Jun Koyama (Sagamihara, JP); Hiroyuki Miyake (Atsugi, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L27/1251H01L27/1225H01L21/02603H01L29/7869
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Quick Facts
Patent No.
US 9,093,328
App. No.
12/938,533
Granted
Jul 28, 2015
Kind
B2
Abstract

An oxide semiconductor layer which is intrinsic or substantially intrinsic and includes a crystalline region in a surface portion of the oxide semiconductor layer is used for the transistors. An intrinsic or substantially intrinsic semiconductor from which an impurity which is to be an electron donor (donor) is removed from an oxide semiconductor and which has a larger energy gap than a silicon semiconductor is used. Electrical characteristics of the transistors can be controlled by controlling the potential of a pair of conductive films which are provided on opposite sides from each other with respect to the oxide semiconductor layer, each with an insulating film arranged therebetween, so that the position of a channel formed in the oxide semiconductor layer is determined.

Claims (58)

1. A semiconductor device comprising:

a first transistor over a substrate; and

a second transistor over the substrate, the first transistor and the second transistor each comprising:

a first electrode layer;

a first insulating film over the first electrode layer;

an oxide semiconductor layer over the first insulating film, the oxide semiconductor layer comprising indium, zinc, and one or more metal elements selected from gallium, aluminum, manganese, cobalt, and tin;

a second electrode layer on the oxide semiconductor layer, the second electrode layer having a first end portion overlapping with the first electrode layer;

a third electrode layer on the oxide semiconductor layer, the third electrode layer having a second end portion overlapping with the first electrode layer;

a second insulating film including an oxide insulating film, the oxide insulating film in contact with the second electrode layer, the third electrode layer, and the oxide semiconductor layer; and

a fourth electrode layer over the first electrode layer with at least the oxide semiconductor layer and the second insulating film interposed therebetween,

wherein the first electrode layer of the second transistor has an edge portion overlapping with the oxide semiconductor layer of the second transistor,

wherein the oxide semiconductor layer of the second transistor has an edge portion overlapping with the first electrode layer of the second transistor,

wherein the fourth electrode layer of the second transistor is in contact with the second electrode layer of the second transistor in a region in which the first electrode layer of the second transistor overlaps the second electrode layer of the second transistor,

wherein a first region including a surface portion of the oxide semiconductor layer comprises a crystalline region comprising crystals, and

wherein c-axes of the crystals are oriented substantially in a direction perpendicular to the surface portion of the oxide semiconductor layer.

2. The semiconductor device according to claim 1 , wherein the first transistor and the second transistor each further comprising a second region of the oxide semiconductor layer comprising an amorphous region or a mixture region of amorphousness and microcrystals.

3. An inverter circuit comprising the semiconductor device according to claim 1 , wherein the first transistor is a depletion transistor and the second transistor is an enhancement transistor.

4. A driving method of the inverter circuit according to claim 3 ,

wherein the fourth electrode layer is operated as a main gate electrode in the depletion transistor, and

wherein the fourth electrode layer is operated as a main gate electrode in the enhancement transistor.

5. A display device comprising the semiconductor device according to claim 1 , wherein the semiconductor device includes a pixel portion and a driver circuit portion which drives the pixel portion.

6. A driving method of the display device according to claim 5 ,

wherein the first electrode layer is operated as a main gate electrode in the first transistor included in the pixel portion, and

wherein the fourth electrode layer is operated as a main gate electrode in the second transistor included in the driver circuit portion.

7. A driving method of the semiconductor device according to claim 1 ,

wherein the first electrode layer is operated as a main gate electrode in the first transistor, and

wherein the fourth electrode layer is operated as a main gate electrode in the second transistor.

8. The semiconductor device according to claim 1 , wherein an energy gap of an oxide semiconductor included in the oxide semiconductor layer is greater than or equal to 2 eV.

9. A method for manufacturing a first transistor and a second transistor of a semiconductor device comprising the steps of:

forming a first electrode layer;

forming a first insulating film over the first electrode layer;

forming an oxide semiconductor layer over the first insulating film, the oxide semiconductor layer comprising indium, zinc, and one or more metal elements selected from gallium, aluminum, manganese, cobalt, and tin;

performing dehydration or dehydrogenation on the oxide semiconductor layer, so that a crystalline region comprising crystals is formed in a first region including a surface portion of the oxide semiconductor layer;

forming a second electrode layer and a third electrode layer on the oxide semiconductor layer, the second electrode layer having a first end portion overlapping with the first electrode layer, and the third electrode layer having a second end portion overlapping with the first electrode layer;

forming a second insulating film including an oxide insulating film, the oxide insulating film in contact with the second electrode layer, the third electrode layer, and the oxide semiconductor layer; and

forming a fourth electrode layer over the first electrode layer with at least the oxide semiconductor layer and the second insulating film interposed therebetween,

wherein the first electrode layer has an edge portion overlapping with the oxide semiconductor layer,

wherein the oxide semiconductor layer has an edge portion overlapping with the first electrode layer,

wherein the fourth electrode layer is in contact with the second electrode layer in a region in which the first electrode layer overlaps the second electrode layer,

wherein c-axes of the crystals are oriented substantially in a direction perpendicular to the surface portion of the oxide semiconductor layer, and

wherein the first transistor and the second transistor are formed over a substrate.

10. The method for manufacturing the first transistor and the second transistor of the semiconductor device according to claim 9 , wherein the first transistor and the second transistor each further comprising a second region of the oxide semiconductor layer comprising an amorphous region or a mixture region of amorphousness and microcrystals.

11. The method for manufacturing the first transistor and the second transistor of the semiconductor device according to claim 9 ,

wherein an inverter circuit comprising the semiconductor device, and

wherein the first transistor is a depletion transistor and the second transistor is an enhancement transistor.

12. The method for manufacturing the first transistor and the second transistor of the semiconductor device according to claim 11 ,

wherein the fourth electrode layer is operated as a main gate electrode in the depletion transistor; and

wherein the fourth electrode layer is operated as a main gate electrode in the enhancement transistor.

13. The method for manufacturing the first transistor and the second transistor of the semiconductor device according to claim 9 ,

wherein a display device comprising the semiconductor device, and

wherein the semiconductor device includes a pixel portion and a driver circuit portion which drives the pixel portion.

14. The method for manufacturing the first transistor and the second transistor of the semiconductor device according to claim 13 ,

wherein the first electrode layer is operated as a main gate electrode in the first transistor included in the pixel portion, and

wherein the fourth electrode layer is operated as a main gate electrode in the second transistor included in the driver circuit portion.

15. The method for manufacturing the first transistor and the second transistor of the semiconductor device according to claim 9 ,

wherein the first electrode layer is operated as a main gate electrode in the first transistor, and

wherein the fourth electrode layer is operated as a main gate electrode in the second transistor.

16. The method for manufacturing the first transistor and the second transistor of the semiconductor device according to claim 9 , wherein an energy gap of an oxide semiconductor included in the oxide semiconductor layer is greater than or equal to 2 eV.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 3, 2010
From: YAMAZAKI, SHUNPEI; KOYAMA, JUN; MIYAKE, HIROYUKI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 025240/0625 →
Priority Claims (1)
JP 2009-255535 · Nov 6, 2009 · national
Continuity (1)
Related Publication 20110109351A1 · May 12, 2011