Liquid crystal display device with influences of offset voltages reduced
View Patent ↗A semiconductor integrated circuit includes a first register, a second register, a gray scale voltage generator which outputs a plurality of gray scale voltages, a decoder which selects a gray scale voltage, and an amplifier including a first transistor, a second transistor, a third transistor, and a fourth transistor. A first terminal of the first transistor and a first terminal of the second transistors are connected to a first voltage line, a first terminal of the third transistor and a first terminal of the fourth transistor are connected to a second voltage line, a second terminal of the first transistor is connected to a second terminal of the third transistor, and a second terminal of the second transistor is connected to a second terminal of the fourth transistor.
1. A semiconductor integrated circuit comprising:
a first register which latches display data;
a second register which latches the display data of the first register in accordance with a first clock;
a gray scale voltage generator which outputs a plurality of gray scale voltages;
a decoder which selects a gray scale voltage in accordance with the display data of the second register from the plurality of gray scale voltages; and
an amplifier including a first transistor, a second transistor, a third transistor, and a fourth transistor;
wherein a first terminal of the first transistor and a first terminal of the second transistors are connected to a first voltage line, a first terminal of the third transistor and a first terminal of the fourth transistor are connected to a second voltage line, a second terminal of the first transistor is connected to a second terminal of the third transistor, and a second terminal of the second transistor is connected to a second terminal of the fourth transistor; and
wherein the gray scale voltage outputted from the decoder is supplied to one of input terminals of the first transistor and the second transistor in accordance with a control signal.
2. A semiconductor integrated circuit according to claim 1 , wherein an output of the amplifier is supplied to other input terminals of the first transistor and the second transistor.
3. A semiconductor integrated circuit according to claim 2 , wherein the first transistor and the second transistor are PMOS transistors, and the third transistor and the fourth transistor are NMOS transistors.
4. A semiconductor integrated circuit according to claim 1 , wherein a phase of the control signal is reversed at intervals of two frame periods.
5. A semiconductor integrated circuit according to claim 4 , wherein an output of the amplifier is supplied to other input terminals of the first transistor and the second transistor.
6. A semiconductor integrated circuit according to claim 5 , wherein the first transistor and the second transistor are PMOS transistors, and the third transistor and the fourth transistor are NMOS transistors.
7. A semiconductor integrated circuit according to claim 1 , wherein a phase of the control signal is reversed at intervals of two cycles of the first clock.
8. A semiconductor integrated circuit according to claim 7 , wherein an output of the amplifier is supplied to other input terminals of the first transistor and the second transistor.
9. A semiconductor integrated circuit according to claim 8 , wherein the first transistor and the second transistor are PMOS transistors, and the third transistor and the fourth transistor are NMOS transistors.
10. A semiconductor integrated circuit according to claim 1 , wherein a frequency of the first clock is more than a frequency of the control signal.
11. A semiconductor integrated circuit according to claim 10 , wherein an output of the amplifier is supplied to other input terminals of the first transistor and the second transistor.
12. A semiconductor integrated circuit according to claim 11 , wherein the first transistor and the second transistor are PMOS transistors, and the third transistor and the fourth transistor are NMOS transistors.