IP Library Granted Patent US 8,971,326
Granted Patent B2
US 8,971,326 · App. 12/939,508 · Granted Mar 3, 2015

Apparatus and method for hardware payload header suppression, expansion, and verification

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Quick Facts
Patent No.
US 8,971,326
App. No.
12/939,508
Granted
Mar 3, 2015
Kind
B2
Abstract

The present invention provides methods for performing payload header suppression (PHS), expansion, and verification in hardware. A PHS verify circuit reads a data packet until it reaches the location where the first byte must be compared to PHS rule verify bytes. Next, all the relevant bytes in the payload header are compared to the PHS vile verify bytes obtained from a payload header suppression rule mask. Upon completion of the compare, a flag is generated to a PHS suppress circuit indicating that verification has passed or failed. For payload headers passing the verification process, the payload header suppress circuit examines the payload header suppression mask to identify one or more bits in the payload header for which an associated byte string is to be suppressed. Next, the associated byte string for each of the identified bits are suppressed to generate a suppressed packet payload header. Finally, a payload header suppression index is added to the suppressed packet payload header. The data packet, including the suppressed packet header and suppression index are then transmitted. Once received, a payload header suppress circuit on the receiver end examines the payload header suppression index to determine if the payload header has been suppressed. For each suppressed payload header, each bit in the payload header is compared to a payload header suppression mask to determine if the bit has been suppressed. Next, for each suppressed bit, a byte string is retrieved from a payload header suppression rule and inserted into the suppressed payload header.

Claims (50)

1. A method for performing payload header suppression in a communications system, the method comprising:

comparing a first header value, from among a plurality of header values, of a data packet to a first mask value from among a plurality of mask values;

setting a first verification indication from among a plurality of verification indications when the first header value is equal to the first mask value;

advancing the first mask value to a second mask value from among the plurality of mask values and the first header value to a second header value, from among the plurality of header values, of the data packet;

comparing the second header value to the second mask value;

setting a second verification indication from among the plurality of verification indications when the second header value is equal to the second mask value; and

suppressing the plurality of header values according to the first and second mask values when the first and the second verification indications are set.

2. The method of claim 1 , further comprising:

retrieving a payload header suppression rule including the plurality of mask values.

3. The method of claim 2 , wherein the retrieving comprises:

retrieving the payload header suppression rule corresponding to a service flow.

4. The method of claim 1 , further comprising:

verifying the plurality of header values are equal to expected values as defined in a payload header suppression rule.

5. The method of claim 1 , further comprising:

advancing the plurality of mask values until the first mask value corresponds to a first logical value, and wherein the comparing the first header value comprises:

comparing the first header value to the first mask value when the first logical value is encountered.

6. The method of claim 5 , wherein the first logical value corresponds to a logical one.

7. The method of claim 1 , further comprising:

activating a suppress enable bit to indicate that the plurality of header values are to be suppressed when the first and the second verification indications are set.

8. The method of claim 1 , further comprising:

appending a payload header suppression index to a payload header having the plurality of header values indicating that the payload header has been suppressed.

9. The method of claim 1 , further comprising:

providing the data packet having the plurality of header values for transmission.

10. The method of claim 1 , further comprising:

isolating a header having the plurality of header values and a payload from the data packet.

11. An apparatus for performing payload header suppression in a communications system, the apparatus comprising:

a payload header suppression verify circuit configured to:

compare a first header value, from among a plurality of header values, of a data packet to a first mask value from among a plurality of mask values,

set a first verification indication from among a plurality of verification indications when the first header value is equal to the first mask value,

advance the first mask value to a second mask value from among the plurality of mask values and the first header value to a second header value, from among the plurality of header values, of the data packet,

compare the second header value to the second mask value,

set a second verification indication from among the plurality of verification indications when the second header value is equal to the second mask value, and

a payload header suppression circuit configured to suppress the plurality of header values according to the plurality of mask values when the first and the second corresponding verification indications are set.

12. The apparatus of claim 11 , wherein the payload header suppression verify circuit comprises:

a mask register configured to store the first mask value;

a descriptor register configured to store the first header value; and

a comparator configured to compare the first header value to the first mask value and to set the first verification indication when the first header value is equal to the first mask value.

13. The apparatus of claim 12 , wherein the payload header suppression verify circuit further comprises:

a state machine configured to cause the mask register and the descriptor register to advance until the first mask value corresponds to a first logical value.

14. The apparatus of claim 13 , wherein the first logical value corresponds to a logical one.

15. The apparatus of claim 11 , further comprising:

a payload header suppression rule fetch circuit configured to retrieve a payload header suppression rule including the plurality of mask values.

16. The apparatus of claim 15 , wherein the payload header suppression rule fetch circuit is further configured to retrieve the payload header suppression rule corresponding to a service flow.

17. The apparatus of claim 11 , wherein the payload header suppression verify circuit is further configured to:

verify the plurality of header values are equal to expected values as defined in a payload header suppression rule.

18. The apparatus of claim 11 , wherein the payload header suppression verify circuit is further configured to:

activate a suppress enable bit to indicate that the plurality of header values are to be suppressed when the first and the second verification indications are set.

19. The apparatus of claim 11 , wherein the payload header suppression verify circuit is further configured to append a payload header suppression index to a payload header having the plurality of header values indicating that the payload header has been suppressed.

20. The apparatus of claim 11 , further comprising:

a description and payload fetch circuit configured to isolate a header having the plurality of header values and a payload from the data packet.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT NUMBER 9,385,856 TO 9,385,756 PREVIOUSLY RECORDED AT REEL: 47349 FRAME: 001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 051144/0648 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE PREVIOUSLY RECORDED ON REEL 047229 FRAME 0408. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047349/0001 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047229/0408 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 4, 2010
From: LANSING, SHANE P.; AVAKIAN, HERATCH
To: BROADCOM CORPORATION
Reel/Frame 025312/0674 →