IP Library Granted Patent US 8,030,186
Granted Patent B2
US 8,030,186 · App. 12/940,789 · Granted Oct 4, 2011

Large-area nanoenabled macroelectronic substrates and uses therefor

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,030,186
App. No.
12/940,789
Granted
Oct 4, 2011
Kind
B2
Abstract

A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.

Claims (9)

1. A method of fabricating nanowires having reduced surface scattering, comprising:

(A) selecting a semiconductor material;

(B) forming a plurality of nanowires from the selected semiconductor material;

(C) oxidizing a circumferential surface of each nanowire of the plurality of nanowires to create a plurality of oxidized nanowires; and

(D) annealing each oxidized nanowire of the plurality of oxidized nanowires.

2. The method of claim 1 , wherein step (D) comprises:

annealing each oxidized nanowire in an H 2 environment to passivate dangling bonds at the interface of an oxidized layer and a non-oxidized portion of each oxidized nanowire.

3. The method of claim 1 , wherein the semiconductor material comprises silicon which is oxidized in step (C) to create an oxide layer of SiO 2 on the plurality of silicon nanowires.

4. The method of claim 3 , further comprising the step of nitriding the silicon dioxide layer to form an oxynitride coating on the plurality of nanowires.

Assignments (9)
PATENT SECURITY AGREEMENT Recorded Jul 26, 2024
From: ONED MATERIAL, INC.
To: VOLTA ENERGY TECHNOLOGIES, LLC, AS COLLATERAL AGENT
Reel/Frame 068174/0120 →
CHANGE OF NAME Recorded Jul 31, 2020
From: ONED MATERIAL LLC
To: ONED MATERIAL, INC.
Reel/Frame 053375/0462 →
RELEASE OF SECURITY INTEREST Recorded Oct 15, 2016
From: MPEG LA, L.L.C
To: ONED MATERIAL LLC
Reel/Frame 040373/0380 →
RELEASE OF SECURITY INTEREST Recorded Oct 15, 2016
From: MPEG LA, L.L.C
To: ONED MATERIAL LLC
Reel/Frame 040373/0484 →
SECURITY INTEREST Recorded Nov 5, 2014
From: ONED MATERIAL LLC
To: MPEG LA, L.L.C.
Reel/Frame 034171/0227 →
SECURITY INTEREST Recorded Mar 14, 2014
From: ONED MATERIAL LLC
To: MPEG LA, L.L.C.
Reel/Frame 032447/0937 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 13, 2014
From: NANOSYS, INC.
To: ONED MATERIAL LLC
Reel/Frame 032264/0148 →
RELEASE OF SECURITY INTEREST Recorded Jun 12, 2013
From: NANOSYS, INC.
To: NANOSYS, INC.
Reel/Frame 030599/0907 →
SECURITY AGREEMENT Recorded Apr 25, 2013
From: PRVP HOLDINGS, LLC
To: NANOSYS, INC.
Reel/Frame 030285/0829 →