Area optimized output impedance controlled driver
View Patent ↗The present invention significantly reduces the chip size of a metal-oxide-semiconductor (MOS) field-effect transistor, which serves as a driver for output impedance drivers, such as, but not limited to, double data rate (DDR2) synchronous dynamic random access memory (SDRAM). In an embodiment of the invention, a voltage drop across the driver is a decreased ratio of the supply voltage, e.g., three-tenths of the supply voltage, lower than half of the supply voltage. A smaller voltage drop allows a lower current and a higher impedance to be used in the driver. By having a higher impedance across the driver, the physical area needed for the DDR2 driver is reduced because a transistor with a smaller physical width can be used. A DDR2 driver operating at the decreased ratio is the functional equivalent of the driver operating with the supply voltage or half of the supply voltage, with the added advantage of the reduced area.
1. A device comprising:
a reference voltage set to be a supply voltage or half of the supply voltage;
one or more external resistors connected in series with the reference voltage, the one or more external resistors having one or more impedance values; and
a driver connected in series with the external resistors, the driver having an equivalent impedance value and a voltage drop across the driver,
wherein a first value for the one or more impedance values and a second value for the equivalent impedance value are calculated with the voltage drop being a voltage drop of half of the supply voltage,
wherein the one or more impedance values are set larger than the first value and the equivalent impedance value is set larger than the second value with the voltage drop being less than half of the supply voltage.
2. The device of claim 1 , further comprising a minimum current corresponding to the voltage drop of half of the supply voltage, wherein a current through the driver is less than the minimum current.
3. The device of claim 1 , wherein the one or more impedance values are set four times larger than the first value and the equivalent impedance value is set four times larger than the second value.
4. The device of claim 1 , wherein the driver comprises two impedances.
5. The device of claim 4 , wherein the two impedances comprise an in series on-chip impedance and a transistor impedance.
6. The device of claim 5 , wherein the transistor impedance is calibrated iteratively based on the in series on-chip impedance and the one or more external resistors.
7. The device of claim 1 , wherein the one or more external resistors comprises two resistors when the reference voltage is the supply voltage.
8. The device of claim 7 , wherein the two resistors connect to a comparator for calibrating the equivalent impedance value.
9. The device of claim 1 , wherein the voltage drop is determined by a JEDEC SSTL — 18 standard.
10. A method comprising:
setting a reference voltage to be a supply voltage or half of the supply voltage;
using one or more external resistors connected in series with the reference voltage, the one or more external resistors having one or more impedance values;
using a driver connected in series with the external resistors, the driver having an equivalent impedance value and a voltage drop across the driver;
calculating a first value for the one or more impedance values and a second value for the equivalent impedance value with the voltage drop being a voltage drop of half of the supply voltage; and
setting the one or more impedance values larger than the first value and the equivalent impedance value larger than the second value with the voltage drop being less than half of the supply voltage.
11. The method of claim 10 , further comprising a minimum current corresponding to the voltage drop of half of the supply voltage, wherein a current through the driver is less than the minimum current.
12. The method of claim 10 , wherein the one or more impedance values are set four times larger than the first standard value and the equivalent impedance value is set four times larger than the second standard value.
13. The method of claim 10 , wherein the driver comprises two impedances.
14. The method of claim 13 , wherein the two impedances comprise an in series on-chip impedance and a transistor impedance.
15. The method of claim 14 , wherein the transistor impedance is calibrated iteratively based on the in series on-chip impedance and the one or more external resistors.
16. The method of claim 10 , wherein the one or more external resistors comprises two resistors when the reference voltage is the supply voltage.
17. The method of claim 16 , wherein the two resistors connect to a comparator for calibrating the equivalent impedance value.
18. The method of claim 10 , wherein the voltage drop is determined by a JEDEC SSTL — 18 standard.