DISPLAY PANEL

1 . A display panel, comprising:

a display area comprising a gate line and a data line;

a gate driver on a substrate and connected to one end of the gate line, the gate driver comprising a plurality of a stage;

a signal line connected to the stages; and

a blocking member disposed on the signal line and overlapped with the signal line, the blocking member comprising a plurality of an opening.

2 . The display panel of claim 1 , wherein:

the signal line is disposed at the same layer as the gate line or the data line.

3 . The display panel of claim 1 , wherein:

direct current voltage is applied to the blocking member.

4 . The display panel of claim 3 , wherein:

the direct current voltage is low voltage.

5 . The display panel of claim 1 , wherein:

the signal line comprises at least one of a scan signal line and a clock signal line.

6 . The display panel of claim 5 , wherein:

each of the stages comprises a clock input terminal, and the clock signal line is connected to the clock input terminal.

7 . The display panel of claim 5 , wherein:

the signal line comprises a voltage signal line which applies low voltage.

8 . The display panel of claim 7 , wherein:

each of the stages comprises a voltage input terminal, and the voltage signal line is connected to the voltage input terminal.

9 . The display panel of claim 1 , further comprising:

a signal controller controlling the gate driver, wherein the signal line connects the gate driver with the signal controller.

10 . The display panel of claim 1 , wherein:

the blocking member is arranged in a mesh shape in a plan view of the display panel.

11 . The display panel of claim 1 , wherein:

the openings of the blocking member are disposed at a first region where the signal line and the blocking member are overlapped with each other.

12 . The display panel of claim 11 , wherein:

the openings of the blocking member are disposed at a second region where the signal line and the blocking member are not overlapped with each other.

13 . The display panel of claim 11 , wherein:

the openings of the blocking member are not disposed at a second region where the signal line and the blocking member are not overlapped with each other.

14 . The display panel of claim 1 , wherein:

the blocking member comprises a transparent conductive material.

15 . The display panel of claim 1 , further comprising:

a pixel electrode disposed on the gate line and the data line, wherein the blocking member is disposed at the same layer as the pixel electrode.

16 . The display panel of claim 1 , further comprising:

a data driver applying data voltage to the data line,

wherein

the signal line comprises a data signal line connected to the data driver, and

wherein the blocking member is disposed on the data signal line and is overlapped with the data signal line.

17 . The display panel of claim 16 , wherein:

the data signal line comprises at least one of a negative data signal line and a positive data signal line.

18 . The display panel of claim 16 , further comprising:

a signal controller controlling the data driver, wherein the data signal line connects the data driver with the signal controller.

19 . The display panel of claim 16 , wherein:

the openings of the blocking member are disposed at a third region where the data signal line and the blocking member are overlapped with each other.

20 . The display panel of claim 19 , wherein:

the openings of the blocking member are disposed at a fourth region where the data signal line and the blocking member are not overlapped with each other.

21 . The display panel of claim 19 , wherein:

the plurality of openings of the blocking member are not disposed at a fourth region where the data signal line and the blocking member are not overlapped with each other.

22 . The display panel of claim 1 , wherein:

each of the stages comprises a first input terminal, a second input terminal, an output terminal, and a transmission signal output terminal, and

the stages comprise a first stage and a second stage,

wherein a transmission signal output terminal of the first stage is connected to a first input terminal of the second stage, and a second input terminal of the first stage is connected to an output terminal of the second stage.

23 . The display panel of claim 22 , wherein:

the signal line comprises a scan start signal line connected to the first input terminal of the first stage.

24 . The display panel of claim 22 , wherein:

each of the stages comprises an input unit, a pull-up driving unit, a pull-down driving unit, an output unit, and a transmission signal generation unit.

25 . The display panel of claim 24 , wherein:

the input unit, the pull-down driving unit, the output unit, and the transmission signal generation unit are connected to a first node.

26 . A method of forming a display panel, the method comprising:

forming a gate line and a data line on a display area of a substrate;

disposing a gate driver in a non-display area of the substrate, and connected to the gate line, the gate driver including a plurality of a stage;

forming a first signal line on the substrate and connecting the first signal line to the stages of the gate driver;

disposing a single unitary indivisible blocking member including a plurality of an opening, overlapping with the first signal line.

27 . The method of claim 26 , further comprising:

connecting a signal controller to the gate driver, wherein the first signal line connects the gate driver to the signal controller.

28 . The method of claim 27 , further comprising:

connecting the signal controller to a data driver, wherein a second signal line different from the first signal line connects the signal controller to the data driver; and

the disposing a single unitary indivisible blocking member includes overlapping the blocking member with the second signal line.