IP Library Granted Patent US 8,886,957
Granted Patent B2
US 8,886,957 · App. 12/942,986 · Granted Nov 11, 2014

Systems, methods, software, and components using tamper-proof real-time clock

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,886,957
App. No.
12/942,986
Granted
Nov 11, 2014
Kind
B2
Abstract

The write-access control line for an RTC is combined with a clear line for an RTC signature register, so that changes to the RTC will cause subsequent reads to return an invalidity flag.

Claims (26)

1. A device, comprising:

instruction execution logic operable to execute a plurality of software instructions;

a real-time clock configured to maintain and provide a system time;

a signature storage register having a write-access control line inaccessible to a user, wherein the signature storage register is configured to hold a digital signature for the real-time clock generated by digital rights management software when a software license is granted, wherein the signature storage register includes an invalidation control line connected to the real-time clock;

wherein the invalidation control line forces the signature register into an invalid state whenever the write-access control line goes active.

2. The device of claim 1 , wherein the real-time clock is configured to maintain the system time in nonvolatile memory.

3. The device of claim 1 , wherein the digital signature is cleared when the system time is modified.

4. The device of claim 1 , wherein the signature storage register is write only.

5. The device of claim 1 , wherein digital rights management (DRM) software verifies the digital signature by generating a new signature for the real-time clock and determining if the new signature corresponds to the digital signature maintained in the signature storage register.

6. The device of claim 1 , wherein the digital signature is generated based on a unique hardware-encoded value.

7. The device of claim 1 , wherein the digital signature is generated based on a unique hardware-encoded value and a current system time.

8. The device of claim 1 , wherein the invalidation control line is a clear input.

9. The device of claim 1 , wherein the invalidation control line is electrically connected to the write-access control line.

10. A method, comprising:

receiving a software license grant;

generating a digital signature for a real-time clock configured to maintain and provide a system time;

storing the digital signature in a signature storage register having a write-access control line inaccessible to a user, wherein the signature storage register is configured to hold a digital signature for the real-time clock, wherein the signature storage register includes an invalidation control line connected to the real-time clock;

wherein the invalidation control line forces the signature register into an invalid state whenever the write-access control line goes active.

11. The method of claim 10 , wherein the real-time clock is configured to maintain the system time in nonvolatile memory.

12. The method of claim 10 , wherein the digital signature is cleared when the system time is modified.

13. The method of claim 10 , wherein the signature storage register is write only.

14. The method of claim 10 , wherein digital rights management (DRM) software verifies the digital signature by generating a new signature for the real-time clock and determining if the new signature corresponds to the digital signature maintained in the signature storage register.

15. The method of claim 10 , wherein the digital signature is generated based on a unique hardware-encoded value.

16. The method of claim 10 , wherein the digital signature is generated based on a unique hardware-encoded value and a current system time.

17. The method of claim 10 , wherein the invalidation control line is a clear input.

18. The method of claim 10 , wherein the invalidation control line is electrically connected to the write-access control line.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Oct 26, 2020
From: JEFFERIES FINANCE LLC
To: RPX CORPORATION
Reel/Frame 054486/0422 →
SECURITY INTEREST Recorded Jun 29, 2018
From: RPX CORPORATION
To: JEFFERIES FINANCE LLC
Reel/Frame 046486/0433 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 16, 2017
From: ZIILABS INC., LTD.
To: RPX CORPORATION
Reel/Frame 044476/0749 →
CHANGE OF NAME Recorded Nov 25, 2014
From: 3DLABS INC., LTD.
To: ZIILABS INC., LTD.
Reel/Frame 034467/0399 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 28, 2011
From: BLOOMFIELD, JONATHAN; MURPHY, NICHOLAS
To: 3DLABS INC. LTD.
Reel/Frame 026033/0865 →