Voltage equalization for stacked FETs in RF switches
A switch branch that improves voltage uniformity across a series stack of an n-number of transistors is disclosed. A first one of the n-number of transistors is coupled to an input terminal, and an nth one of the n-number of transistors is coupled to an output terminal, where n is a positive integer greater than one. Predetermined parasitic capacitances associated with each of the n-number of transistors are adjustable with respect to capacitance value by predetermined amounts by dimensioning and arranging at least one metal layer element in proximity to the series stack of the n-number of transistors. Capacitance values for the predetermined parasitic capacitances are selected such that a voltage across the series stack of the n-number of transistors is uniformly distributed. In this way, the n-number of transistors can be reduced without risking a transistor breakdown within the series stack of the n-number of transistors.
1. A switch branch, comprising:
an input terminal, an output terminal, and a series stack of N transistors in a first plane, wherein N is a positive number greater than one and a first one of the N transistors is coupled to the input terminal, and an Nth one of the N transistors is coupled to the output terminal;
N+1 metal stripes that reside in and are spaced apart from each other in a second plane that is parallel with and above the first plane; and
at least one metal stripe in a third plane that is parallel with and above the second plane, wherein the at least one metal stripe and the N+1 metal stripes are sized and spaced apart from each other to set parasitic drain to source capacitances associated with each of the N transistors such that a voltage drop across each of the N transistors ranges no more than 4% higher to no more that 2% lower than exactly uniform drain to source voltages across each of the N transistors.
2. The switch branch of claim 1 wherein the spacing between a first pair of N+1 metal stripes and a second pair of N+1 metal stripes is different.
3. The switch branch of claim 2 wherein the size of a first of the N+1 metal stripes and a second of the N+1 metal stripes is different.
4. The switch branch of claim 3 wherein the spacing between each of the N transistors is substantially equal.
5. The switch branch of claim 1 wherein the spacing between each of the N transistors is substantially equal.
6. The switch branch of claim 1 wherein the size of a first of the N+1 metal stripes and a second of the N+1 metal stripes is different.
7. The switch branch of claim 1 wherein the at least one metal stripe comprises a plurality of metal stripes in the third plane.
8. The switch branch of claim 7 wherein at least two of the plurality of metal stripes are of different sizes.
9. The switch branch of claim 8 wherein the spacing between a first pair of the plurality of metal stripes and a second pair of the plurality of metal stripes is different.
10. The switch branch of claim 9 wherein the spacing between a first pair of the N+1 metal stripes and a second pair of the N+1 metal stripes is different.
11. The switch branch of claim 10 wherein the size of a first of the N+1 metal stripes and a second of the N+1 metal stripes is different.
12. The switch branch of claim 11 wherein the spacing between each of the N transistors is substantially equal.
13. A method of fabricating a switch branch, comprising:
fabricating a series stack of N transistors in a first plane, wherein N is a positive number greater than one and a first one of the N transistors is coupled to an input terminal, and an Nth one of the N transistors is coupled to an output terminal;
fabricating N+1 metal stripes that reside in and are spaced apart from each other in a second plane that is parallel with and above the first plane; and
fabricating at least one metal stripe in a third plane that is parallel with and above the second plane, wherein the at least one metal stripe and the N+1 metal stripes are sized and spaced apart from each other to set parasitic drain to source capacitances associated with each of the N transistors such that a voltage drop across each of the N transistors ranges no more than 4% higher to no more that 2% lower than exactly uniform drain to source voltages across each of the N transistors.
14. The method of fabricating the switch branch of claim 13 wherein the spacing between a first pair of the N+1 metal stripes and a second pair of the N+1 metal stripes is different.
15. The method of fabricating the switch branch of claim 14 wherein the size of a first of the N+1 metal stripes and a second of the N+1 metal stripes is different.
16. The method of fabricating the switch branch of claim 15 wherein the spacing between each of the N transistors is substantially equal.
17. The method of fabricating the switch branch of claim 13 wherein the spacing between each of the N transistors is substantially equal.
18. The method of fabricating the switch branch of claim 13 wherein the size of a first of the N+1 metal stripes and a second of the N+1 metal stripes is different.
19. The method of fabricating the switch branch of claim 13 wherein the at least one metal stripe comprises a plurality of metal stripes in the third plane.
20. The method of fabricating the switch branch of claim 19 wherein at least two of the plurality of metal stripes are of different sizes.
21. The method of fabricating the switch branch of claim 20 wherein the spacing between a first pair of the plurality of metal stripes and a second pair of the plurality of metal stripes is different.
22. The method of fabricating the switch branch of claim 21 wherein the spacing between a first pair of N+1 metal stripes and a second pair of N+1 metal stripes is different.
23. The method of fabricating the switch branch of claim 22 wherein the size of a first of the N+1 metal stripes and a second of the N+1 metal stripes is different.
24. The method of fabricating the switch branch of claim 23 wherein the spacing between each of the N transistors is substantially equal.