Stable current source for system integration to display substrate

1. A high output impedance current source or sink circuit for a light-emitting display, the circuit comprising:

an input that receives a fixed reference current and provides the reference current to a node in the current source or sink circuit during a calibration operation of the current source or sink circuit;

a first transistor and a second transistor series-connected to the node such that the reference current adjusts the voltage at the node to allow the reference current to pass through the series-connected transistors during the calibration operation;

one or more storage devices connected to the node; and

an output transistor connected to the node to source or sink an output current from current stored in the one or more storage devices to drive an active matrix display with a bias current corresponding to the output current.

2. The circuit of claim 1 , further comprising an output control line connected to a gate of the output transistor for controlling whether the output current is available to drive the active matrix display.

3. The circuit of claim 1 , wherein the one or more storage devices includes a first storage device connected between the node and the first transistor and a second storage device connected between the node and the second transistor.

4. The circuit of claim 1 , wherein the one or more storage devices includes a first storage device connected between the node and the first transistor and a second storage device connected between the first transistor and a gate of the second transistor.

5. The circuit of claim 1 , further comprising:

a first voltage switching transistor controlled by a calibration access control line and connected to the first transistor;

a second voltage switching transistor controlled by the calibration access control line and connected to the second transistor; and

an input transistor controlled by the calibration access control line and connected between the node and the input.

6. The circuit of claim 5 , wherein the calibration access control line is activated to initiate the calibration operation of the circuit followed by activating an access control line to initiate the programming of a column of pixels of the active matrix display using the bias current.

7. The circuit of claim 1 , wherein the one or more storage devices includes a first capacitor and a second capacitor, the circuit further comprising:

an input transistor connected between the input and the node;

a first voltage switching transistor connected to the first transistor, the second transistor, and the second capacitor;

a second voltage switching transistor connected to the node, the first transistor, and the first transistor; and

a gate control signal line connected to the gates of the input transistor, the first voltage switching transistor, and the second voltage switching transistor.

8. The circuit of claim 1 , further comprising a reference current source external to the active matrix display and supplying the reference current.

9. The circuit of claim 1 , further comprising:

an input transistor connected between the input and the node;

a gate control signal line connected to the gate of the input transistor; and

a voltage switching transistor having a gate connected to the gate control signal line and connected to the second transistor and the one or more storage devices.

10. The circuit of claim 1 , wherein the first transistor, the second transistor, and the output transistor are p-type field effect transistors having respective gates, sources, and drains, wherein the one or more storage devices includes a first capacitor and a second capacitor, wherein the drain of the first transistor is connected to the source of the second transistor, and the gate of the first transistor is connected to the first capacitor, and wherein the drain of the output transistor is connected to the node, and the source of the output transistor sinks the output current.

11. The circuit of claim 10 , further comprising:

a first voltage switching transistor having a gate connected to a calibration control line, a drain connected to a first voltage supply, and a source connected to the first capacitor;

a second voltage switching transistor having a gate connected to the calibration control line, a drain connected to a second voltage supply, and a source connected to the second capacitor; and

an input transistor having a gate connected to the calibration control line, a drain connected to the node, and a source connected to the input,

wherein the gate of the output transistor is connected to an access control line, and the first voltage switching transistor, the second voltage switching transistor, and the input transistor being p-type field effect transistors.

12. The circuit of claim 11 , wherein the second capacitor is connected between the gate of the second transistor and the node.

13. The circuit of claim 1 , further comprising a second capacitor connected between the gate of the second transistor and the source of the second transistor.

14. The circuit of claim 1 , wherein the first transistor, the second transistor, and the output transistor are n-type field effect transistors having respective gates, sources, and drains, wherein the one or more storage devices includes a first capacitor, wherein the source of the first transistor is connected to the drain of the second transistor, and the gate of the first transistor is connected to the first capacitor, the first capacitor being connected to the node through the first transistor, and wherein the source of the output transistor is connected to the node, and the drain of the output transistor sinks the output current.

15. The circuit of claim 14 , further comprising:

a first voltage switching transistor having a gate connected to a gate control signal line, a drain connected to the node, and a source connected to the first capacitor and to the first transistor;

a second voltage switching transistor having a gate connected to the gate control signal line, a drain connected to the source of the first transistor, and a source connected to the gate of the second transistor; and

an input transistor having a gate connected to the gate control signal line, a source connected to the node, and a drain connected to the input,

wherein the gate of the output transistor is connected to an access control line, and the first voltage switching transistor, the second voltage switching transistor, and the input transistor are n-type field effect transistors.

16. The circuit of claim 1 , wherein the first transistor, the second transistor, and the output transistor are p-type field effect transistors having respective gates, sources, and drains, wherein the one or more storage devices includes a first capacitor, wherein the drain of the first transistor is connected to the source of the second transistor, and the gate of the first transistor is connected to the first capacitor, and wherein the drain of the output transistor is connected to the node, and the source of the output transistor sinks the output current.

17. The circuit of claim 16 , further comprising:

an input transistor connected between the node and the input, wherein a drain of the input transistor is connected to a reference current source and a source of the input transistor is connected to the node, a gate of the input transistor being connected to a gate control signal line;

a voltage switching transistor having a gate connected to the gate control signal line, a source connected to the gate of the second transistor, and a drain connected to a ground potential;

wherein the gate of the output transistor is connected to an access control line, and wherein the first capacitor is connected between the gate of the first transistor and the source of the first transistor.

18. A method of sourcing or sinking current to provide a bias current for programming pixels of a light-emitting display, comprising:

initiating a calibration operation of a current source or sink circuit by activating a calibration control line to cause a reference current to be supplied to the current source or sink circuit;

during the calibration operation, storing the current supplied by the reference current in one or more storage devices in the current source or sink circuit;

deactivating the calibration control line while activating an access control line to cause sinking or sourcing of an output current corresponding to the current stored in the one or more storage devices; and

applying the output current to a column of pixels in an active matrix area of the light-emitting display.

19. The method of claim 18 , further comprising applying a first bias voltage and a second bias voltage to the current source or sink circuit, the first bias voltage differing from the second bias voltage to allow the reference current to be copied into the one or more storage devices.

20. A high output impedance current source or sink circuit for a light-emitting display, the circuit comprising:

an input that receives a fixed reference current and provides the reference current to a node in the current source or sink circuit during a calibration operation of the current source or sink circuit;

a first transistor and a second transistor series-connected to the node such that the reference current adjusts the voltage at the node to allow the reference current to pass through the series-connected transistors during the calibration operation;

one or more storage devices connected to a common reference potential and to one or the other or both of the first and the second transistors; and

an output transistor connected to the node to source or sink an output current from current stored in the one or more storage devices to drive an active matrix display with a bias current corresponding to the output current.