Systems, methods and apparatus for local programming of quantum processor elements
View Patent ↗Systems, methods and apparatus for a scalable quantum processor architecture. A quantum processor is locally programmable by providing a memory register with a signal embodying device control parameter(s), converting the signal to an analog signal; and administering the analog signal to one or more programmable devices.
1. A quantum computing system comprising:
an external programming system;
a quantum processor; and
a number of communication lines providing communication between the external programming system and the quantum processor, wherein the quantum processor further comprises:
a number of programmable devices; and
a memory administration system including a plurality of communication conduits, wherein the memory administration system provides communication between the communication lines and at least some of the communication conduits to administer data signals from the external programming system to the programmable devices, and wherein the number of programmable devices is greater than the number of communication lines.
2. The quantum computing system of claim 1 wherein the quantum processor includes at least one programmable device that is formed of a material that is superconducting below a critical temperature.
3. The quantum computing system of claim 1 wherein at least one of the communication conduits of the memory administration system is formed of a material that is superconducting below a critical temperature.
4. The quantum computing system of claim 1 wherein the quantum processor includes at least one programmable device that is selected from the group consisting of: a closed superconducting current path, a compound Josephson junction, a superconducting flux qubit, a superconducting charge qubit, a superconducting phase qubit, a superconducting hybrid qubit, a qubit coupler, a superconducting qubit coupler, a quantum dot, a trapped ion, a trapped neutral atom, an impurity, a nuclear spin qubit, an electronic spin qubit, and a photonic qubit.
5. The quantum computing system of claim 1 wherein the memory administration system includes at least one digital-to-analog converter (DAC).
6. The quantum computing system of claim 5 wherein the DAC includes a superconducting DAC, and wherein digital signals are represented by discrete magnetic flux quanta.
7. The quantum computing system of claim 1 wherein the memory administration system includes an X-Y addressable array.
8. The quantum computing system of claim 1 wherein the memory administration system includes a demultiplexer circuit.
9. A method of programming a quantum processor, wherein the quantum processor includes a number of programmable devices and a memory administration system, the method comprising:
defining a plurality of programmable parameters corresponding to the number of programmable devices by an external programming system;
transmitting a plurality of signals embodying the plurality of programmable parameters from the external programming system to the memory administration system via a number of communication lines that is less than the number of programmable devices; and
administering the plurality of signals embodying the plurality of programmable parameters to the number of programmable devices by the memory administration system.
10. The method of claim 9 wherein the memory administration system includes at least one digital-to-analog converter (DAC) and the plurality of signals embodying the plurality of programmable parameters are digital signals, and further comprising:
converting the plurality of signals embodying the plurality of programmable parameters from digital signals to analog signals by the at least one DAC before administering the plurality of signals embodying the plurality of programmable parameters to the number of programmable devices.
11. The method of claim 9 wherein administering the plurality of signals embodying the plurality of programmable parameters to the number of programmable devices by the memory administration system includes routing the plurality of signals embodying the plurality of programmable parameters to the number of programmable devices via an X-Y addressable array.
12. The method of claim 9 wherein administering the plurality of signals embodying the plurality of programmable parameters to the number of programmable devices by the memory administration system includes routing the plurality of signals embodying the plurality of programmable parameters to the number of programmable devices via a demultiplexer circuit.