Closed loop dynamic interconnect bus allocation method and architecture for a multi layer SoC
View Patent ↗A closed loop dynamic interconnect bus allocation method and architecture for a multi layer SoC is disclosed. In one embodiment, a system on chip (SoC) includes multiple masters, multiple slaves, multiple buses, and an interconnect module coupled to multiple masters and multiple slaves via multiple buses. The interconnect module includes an arbiter. The SoC also includes an inner characteristic bus coupled to the plurality of masters, the plurality of slaves and the interconnect module. The interconnect module receives on-chip bus transactions substantially simultaneously from the multiple masters to be processed on one or more of the multiple slaves via the multiple buses. The interconnect module also receives inner characteristic information of the on-chip bus transactions via the inner characteristic bus. Further, the interconnect module allocates the received on-chip bus transactions from the multiple masters to associated one or more of multiple slaves based on the received inner characteristic information.
1. A method for allocating on chip bus transactions between multiple masters and one or more of multiple slaves in a system on chip (SoC) using inner characteristic information of the on chip bus transactions based on the multiple masters and the multiple slaves, wherein:
the SoC includes the multiple masters, the multiple slaves, and an interconnect module;
the multiple masters and the multiple slaves are connected to the interconnect module via multiple buses;
the multiple masters, the multiple slaves, and the interconnect module are further coupled via an inner characteristic bus, wherein the inner characteristic bus is separate from the multiple buses in the SoC, and the inner characteristic bus does not convey any of the on chip bus transactions from any of the multiple masters; and
allocating the on chip bus transactions comprises:
the interconnect module receiving, via the multiple buses, the on chip bus transactions substantially simultaneously from the multiple masters to be processed on one or more of the multiple slaves;
the interconnect module receiving, via the inner characteristic bus, inner characteristic information of the on chip bus transactions based on the multiple masters and the one or more of the multiple slaves; and
the interconnect module allocating the received on chip bus transactions from the multiple masters to associate one or more of the multiple slaves based on the received inner characteristic information of the on chip bus transactions.
2. The method of claim 1 , wherein the multiple buses include different bus protocols.
3. The method of claim 1 , wherein the inner characteristic information comprises parameters selected from the group consisting of (i) transaction information associated with a current clock, (ii) transaction information associated with one or more subsequent clocks based on the current clock, (iii) transfer size, (iv) data width, (v) protection information, and (vi) first in first out (FIFO) fill or empty level associated with the transaction.
4. The method of claim 1 , further comprising the interconnect module sending feedback associated with the allocation based on the inner characteristic information to the multiple masters and the one or more slaves in the SoC.
5. The method of claim 4 , wherein the feedback comprises information selected from the group consisting of (i) transaction optimization associated with the multiple masters and (ii) slave transaction acceptance.
6. A non transitory computer readable storage medium for allocating on chip bus transactions between multiple masters and multiple slaves via multiple buses in an SoC, having instructions that, when executed by a computing device causes the computing device to perform a method comprising:
receiving the on chip bus transactions substantially simultaneously from the multiple masters to be processed on one or more of the multiple slaves by an interconnect module via the multiple buses;
receiving inner characteristic information of the on chip bus transactions based on the multiple masters and the one or more of the multiple slaves via an inner characteristic bus by the interconnect module, wherein the inner characteristic bus is separate from the multiple buses in the SoC, and the inner characteristic bus does not convey any of the on chip bus transactions from any of the multiple masters; and
allocating the received on chip bus transactions from the multiple masters to associate one or more of the multiple slaves based on the received inner characteristic information of the on chip bus transactions by the interconnect module.
7. The non transitory computer readable storage medium of claim 6 , wherein the inner characteristic information comprises parameters selected from the group consisting of (i) transaction information associated with a current clock, (ii) transaction information associated with one or more subsequent clocks based on the current clock, (iii) transfer size, (iv) data width, (v) protection information, and (vi) FIFO fill or empty level associated with the transaction.
8. The non transitory computer readable storage medium of claim 6 , further comprising sending feedback associated with the allocation based on the inner characteristic information to the multiple masters and the one or more slaves in the SoC.
9. The non transitory computer readable storage medium of claim 8 , wherein the feedback comprises information selected from the group consisting of (i) transaction optimization associated with the multiple masters and (ii) slave transaction acceptance.
10. The non-transitory computer-readable storage medium of claim 6 , wherein the multiple buses include different bus protocols.
11. An SoC, comprising:
multiple masters;
multiple slaves;
multiple buses;
an interconnect module coupled to the multiple masters and the multiple slaves via the multiple buses; and
an inner characteristic bus coupled to the multiple masters, the multiple slaves and the interconnect module, wherein the interconnect module receives on chip bus transactions substantially simultaneously from the multiple masters to be processed on one or more of the multiple slaves via the multiple buses, wherein the inner characteristic bus is separate from the multiple buses in the SoC, and the inner characteristic bus does not convey any of the on chip bus transactions from any of the multiple masters, wherein the interconnect module receives inner characteristic information of the on chip bus transactions based on the multiple masters and the one or more of the multiple slaves via the inner characteristic bus, and wherein the interconnect module allocates the received on chip bus transactions from the multiple masters to associate one or more of the multiple slaves based on the received inner characteristic information of the on chip bus transactions.
12. The SoC of claim 11 , wherein the interconnect module comprises an arbiter.
13. The SoC of claim 12 , wherein the arbiter comprises an inner characteristic information module capable of receiving the inner characteristic information of the on chip bus transactions based on the multiple masters and the one or more of the multiple slaves via the inner characteristic bus.
14. The SoC of claim 11 , wherein the multiple buses include different bus protocols.
15. The SoC of claim 11 , wherein the inner characteristic information comprises parameters selected from the group consisting of (i) transaction information associated with a current clock, (ii) transaction information associated with one or more subsequent clocks based on the current clock, (iii) transfer size, (iv) data width, (v) protection information, and (vi) FIFO fill or empty level associated with the transaction.
16. The SoC of claim 11 , wherein the interconnect module sends feedback associated with the allocation based on the inner characteristic information to the multiple masters and the one or more slaves in the SoC.