Priority logic module
View Patent ↗In a nuclear process control system, a priority logic module (PLM) is provided. The priority logic module comprises a plurality of input ports, each input port associated with one of a plurality of priorities, a plurality of output ports, and a test mode select port associated with a test mode select signal. The test mode select signal selects one of a normal mode or test mode, each mode being associated with matching signals received by the input ports to signals sent by the output ports. The priority logic module further comprises a configurable priority logic circuit, wherein the priority logic circuit maps one of the input ports to one of the output ports.
1. In a nuclear process control system, a priority logic module (PLM), comprising:
a plurality of input ports, each input port associated with one of a plurality of priorities, said plurality of input ports comprising four input ports, each configured to receive an input pair associated with a priority;
a plurality of output ports, said plurality of output ports comprising one output port configured to send one output pair to an actuating device and one test output port configured to send one test output pair to a test device;
a test mode select port associated with a test mode select signal, the test mode select signal selecting one of a normal mode or test mode, each mode being associated with matching signals received by the input ports to signals sent by the output ports;
a configurable priority logic, wherein the priority logic circuit maps one of the input ports to one of the output ports;
wherein the priority logic module is certified for use in a class 1E nuclear process control system, wherein the input ports are configured to receive class 1E signals comprising a plurality of input pairs, and wherein the output ports are configured to send signals comprising a plurality of output pairs;
wherein (Input 1 A, Input 1 B) is the input pair associated with the highest priority input port, wherein (Input 2 A, Input 2 B) is the input pair associated with the second highest priority input port, wherein (Input 3 A, Input 3 B) is the input pair associated with the third highest priority input port, wherein (Input 4 A, Input 4 B) is the input pair associated with the fourth highest priority input port, wherein Test Mode Select is a signal set to ‘0’, wherein (Output 1 A, Output 1 B) is the output pair, wherein (Test Output 1 A, Test Output 1 B) is the test output pair, wherein the output pair and the test output pair are generated from the input pairs, and wherein the following table represents the functional behavior of the priority logic
Input1
Input1
Input2
Input2
Input3
Input3
Input4
Input4
Test Mode
Test
Test
A
B
A
B
A
B
A
B
Select
Output1 A
Output1 B
Output1 A
Output1 B
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
0
0
0
0
1
x
0
1
0
1
0
0
0
0
0
0
1
x
x
0
0
1
0
1
0
0
0
0
1
x
x
x
0
1
0
1
0
0
0
0
1
x
x
x
x
0
0
1
0
1
0
0
1
x
x
x
x
x
0
1
0
1
0
0
1
x
x
x
x
x
x
0
0
1
0
1
1
x
x
x
x
x
x
x
0
1
0
1
0
where ‘1’ indicates a ‘1’ signal, ‘0’ indicates a ‘0’ signal and an ‘x’ indicates a <don't care>.
2. The priority logic module of claim 1 , wherein the priority logic module comprises a complex programmable logic device (CPLD).
3. The priority logic module of claim 1 , wherein the priority logic is a component within the priority logic module, and wherein configuring the priority logic comprises modifying at least one logic component.
4. The priority logic module of claim 1 , wherein the priority logic is configurable at manufacture time.
5. The priority logic module of claim 1 , wherein the priority logic module is not field-programmable.
6. The priority logic module of claim 1 ,wherein the priority logic module further comprises a test output port.
7. The priority logic module of claim 1 , wherein the priority logic module is configured to send at least one output signal produced from the input signal received by the input port associated with the lowest priority.
8. In a nuclear process control system, priority logic module (PLM), comprising:
a plurality of input ports, each input port associated with one of a plurality of priorities, said plurality of input ports comprising four input ports, each configured to receive an input pair associated with a priority;
a plurality of output ports, said plurality of output ports comprising one output port configured to send one output pair to an actuating device and one test output port configured to send one test output pair to a test device;
a test mode select port associated with a test mode select signal, the test mode select signal selecting one of a normal mode or test mode, each mode being associated with matching signals received by the input ports to signals sent by the output ports;
a configurable priority logic, wherein the priority logic circuit maps one of the input ports to one of the output ports;
wherein the priority logic module is certified for use in a class 1E nuclear process control system, wherein the input ports are configured to receive class 1E signals comprising a plurality of input pairs, and wherein the output ports are configured to send signals comprising a plurality of output pairs;
wherein (Input 1 A, Input 1 B) is the input pair associated with the highest priority input port, wherein (Input 2 A, Input 2 B) is the input pair associated with the second highest priority input port, wherein (Input 3 A, Input 3 B) is the input pair associated with the third highest priority input port, wherein (Input 4 A, Input 4 B) is the input pair associated with the fourth highest priority input port, wherein Test Mode Select is a signal set to ‘1’, wherein (Output 1 A, Output 1 B) is the output pair, wherein (Test Output 1 A, Test Output 1 B) is the test output pair, wherein the output pair and the test output pair are generated from the input pairs, and wherein the following tables represent the functional behavior of the priority logic
Test Mode
Test
Test
Input1 A
Input1 B
Input2 A
Input2 B
Input3 A
Input3 B
Input4 A
Input4 B
Select
Output1 A
Output1 B
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
x
1
0
0
0
0
0
0
0
1
x
x
1
0
1
0
0
0
0
1
x
x
x
1
1
0
0
0
0
1
x
x
x
x
1
0
1
0
0
1
x
x
x
x
x
1
1
0
0
1
x
x
x
x
x
x
1
0
1
1
x
x
x
x
x
x
x
1
1
0
Inputs
Outputs
Input4 A
Input4 B
Test Mode Select
Output1 A
Output1 B
0
0
1
0
0
0
1
1
0
1
1
x
1
1
0
where ‘1’ indicates a ‘1’ signal, ‘0’ indicates a ‘0’ signal and an ‘x’ indicates a <don't care>.
9. The priority logic module of claim 8 , wherein the priority logic module comprises a complex programmable logic device (CPLD).
10. The priority logic module of claim 8 , wherein the priority logic is a component within the priority logic module, and wherein configuring the priority logic comprises modifying at least one logic component.
11. The priority logic module of claim 8 , wherein the priority logic is configurable at manufacture time.
12. The priority logic module of claim 8 , wherein the priority logic module is not field-programmable.
13. The priority logic module of claim 8 , wherein the priority logic module further comprises a test output port.
14. The priority logic module of claim 8 , wherein the priority logic module is configured to send at least one output signal produced from the input signal received by the input port associated with the lowest priority.
15. A method for testing, comprising:
selecting a test mode from a test mode select signal;
receiving a plurality of input signals, wherein each input signal is a class 1E signal associated with a priority;
producing at least one output signal from the input signals;
producing an output signal from the lowest priority input signal;
producing a test output signal from the input signals;
sending the output signal to an actuating device;
sending the test output signal to a test device; and
configuring an arbitration logic;
wherein the method is implemented by a priority logic module (PLM), wherein the test mode select signal indicates normal mode or test mode, wherein the input signals comprise a plurality of input pairs, wherein the output signal comprises an output pair and wherein the test output signal comprises a test output pair;
wherein (Input 1 A, Input 1 B) is the input pair associated with the highest priority input port, wherein (Input 2 A, Input 2 B) is the input pair associated with the second highest priority input port, wherein (Input 3 A, Input 3 B) is the input pair associated with the third highest priority input port, wherein (Input 4 A, Input 4 B) is the input pair associated with the fourth highest priority input port, wherein Test Mode Select is a signal set to ‘0’, wherein (Output 1 A, Output 1 B) is the output pair, wherein (Test Output 1 A, Test Output 1 B) is the test output pair, wherein the output pair and the test output pair are generated from the input pairs, and wherein the following table represents the functional behavior of the priority logic
Input3
Input4
Test Mode
Test
Test
Input1 A
Input1 B
Input2 A
Input2 B
A
Input3 B
A
Input4 B
Select
Output1 A
Output1 B
Output1 A
Output1 B
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
0
0
0
0
1
x
0
1
0
1
0
0
0
0
0
0
1
x
x
0
0
1
0
1
0
0
0
0
1
x
x
x
0
1
0
1
0
0
0
0
1
x
x
x
x
0
0
1
0
1
0
0
1
x
x
x
x
x
0
1
0
1
0
0
1
x
x
x
x
x
x
0
0
1
0
1
1
x
x
x
x
x
x
x
0
1
0
1
0
where ‘1’ indicates a ‘1’ signal, ‘0’ indicates a ‘0’ signal and an ‘x’ indicates a <don't care>.
16. A method for testing, comprising:
selecting a test mode from a test mode select signal;
receiving a plurality of input signals, wherein each input signal is a class 1E signal associated with a priority;
producing at least one output signal from the input signals;
producing an output signal from the lowest priority input signal;
producing a test output signal from the input signals;
sending the output signal to an actuating device;
sending the test output signal to a test device; and
configuring an arbitration logic;
wherein the method is implemented by a priority logic module (PLM), wherein the test mode select signal indicates normal mode or test mode, wherein the input signals comprise a plurality of input pairs, wherein the output signal comprises an output pair and wherein the test output signal comprises a test output pair;
wherein (Input 1 A, Input 1 B) is the input pair associated with the highest priority input port, wherein (Input 2 A, Input 2 B) is the input pair associated with the second highest priority input port, wherein (Input 3 A, Input 3 B) is the input pair associated with the third highest priority input port, wherein (Input 4 A, Input 4 B) is the input pair associated with the fourth highest priority input port, wherein Test Mode Select is a signal set to ‘1’, wherein (Output 1 A, Output 1 B) is the output pair, wherein (Test Output 1 A, Test Output 1 B) is the test output pair, wherein the output pair and the test output pair are generated from the input pairs, and wherein the following tables represent the functional behavior of the priority logic
Test Mode
Test
Test
Input1 A
Input1 B
Input2 A
Input2 B
Input3 A
Input3 B
Input4 A
Input4 B
Select
Output1 A
Output1 B
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
x
1
0
0
0
0
0
0
0
1
x
x
1
0
1
0
0
0
0
1
x
x
x
1
1
0
0
0
0
1
x
x
x
x
1
0
1
0
0
1
x
x
x
x
x
1
1
0
0
1
x
x
x
x
x
x
1
0
1
1
x
x
x
x
x
x
x
1
1
0
wherein the functional behavior of the output pair is represented in the following table
Inputs
Outputs
Input4 A
Input4 B
Test Mode Select
Output1 A
Output1 B
0
0
1
0
0
0
1
1
0
1
1
x
1
1
0
where ‘1’ indicates a ‘1’ signal, ‘0’ indicates a ‘0’ signal and an ‘x’ indicates a <don't care>.