Skew management in an interconnection system
View Patent ↗An interconnection system is described where data lanes may be exchanged between lines at intervals along a transmission path so that the differential time delay between bits on a plurality of the lines is reduced when determined at a receiving location. The data lanes may be bound to the lines through the operation of a configurable switch, or by a configurable switch in conjunction with predetermined manufactured connections, or a combination of the techniques. The wiring of a connectorized node module, which may include a memory device, may be configured so that the differential time delay between pairs of input lines of a node, as measured at the output of a node, is reduced.
1. An interconnect system, comprising:
A bus having a plurality of signal lines, each line capable of transmitting a signal comprising a data bit;
wherein a data bit on a first line and a data bit on a second line are exchanged between signal lines at an interval along the bus;
wherein the data is transmitted on three or more signal lines, and the data bits are exchanged such that the data bit having a first cumulative time delay is exchanged with the data bit having a second cumulative time delay;
wherein the data bits are exchanged such that the differential cumulative time delay is changed;
and the change of differential cumulative time delay is measured at a receiving location on the bus.
2. The system of claim 1 , where the cumulative time delay is measured at the output of a data receiver at a receiving end of the signal lines.
3. The system of claim 1 , wherein the first cumulative time delay is greater than the second cumulative time delay.
4. The system of claim 1 , wherein the second cumulative time delay is greater than the first cumulative time delay.
5. The system of claim 1 , wherein an exchange pattern of a first exchange pattern is used for each subsequent exchange.
6. The system of claim 5 , wherein the exchange pattern is effected by conductive traces.
7. The system of claim 6 , wherein the conductive traces are disposed between connectors on a mother board.
8. The system of claim 6 , wherein the conductive traces are disposed on a connectorized module.
9. The system of claim 8 , wherein the conductive traces are disposed in an electronic circuit mounted on the plug in module.
10. The system of claim 1 , wherein an assignment of data bits to lines for data transmitted on the bus is selected such that a desired ordering of data bits is obtained at a receiving location on the bus.
11. The system of claim 1 , wherein the interval is the separation distance between connected nodes.
12. The system of claim 1 , wherein the data bits are exchanged such that the data bit having a larger cumulative time delay is exchanged with the data bit having a smaller cumulative time delay.
13. The system of claim 12 , wherein the data is transmitted on three or more signal lines, and the data bits are exchanged such that the data bit having a largest cumulative time delay is exchanged with the data bit having a smallest cumulative time delay.
14. The system of claim 13 , wherein the cumulative time delay is measured at a receiving end of the signal lines.
15. The system of claim 13 , wherein the cumulative time delay is measured at the output of a data receiver at a receiving end of the signal lines.
16. The system of claim 1 , wherein the data bits are exchanged such that the cumulative time delay difference between data bits on at least a pair of lanes is reduced at a receiving location where the data is to be stored or demultiplexed.