Method and system for error correction in flash memory
View Patent ↗A multi-level solid state non-volatile memory array has memory cells that store data using a first number of digital levels. A controller of the memory array encodes a series of data bits to generate a series of encoded data bits, and converts the series of encoded data bits into a series of data symbols. The controller sends, to the memory array, a stored series of data symbols based on the series of data symbols for storage in a memory cell of the multi-level solid state non-volatile memory array. The controller generates an output signal based on data associated with the stored series of data symbols. The output signal is characterized by a second number of digital levels greater than the first number of digital levels. The controller outputs a series of output data symbols based on the output signal.
1. A controller for a multi-level solid state non-volatile memory array having memory cells, the memory cells adapted to store data using a first number of digital levels, the controller configured to:
encode a series of data bits to generate a series of encoded data bits;
convert the series of encoded data bits into a series of data symbols;
send, to the memory array, a stored series of data symbols based on the series of data symbols for storage in a memory cell of the multi-level solid state non-volatile memory array;
generate an output signal based on data associated with the stored series of data symbols, the output signal characterized by a second number of digital levels greater than the first number of digital levels used to store the series of data symbols in the memory cell; and
output a series of output data symbols based on the output signal.
2. The controller of claim 1 comprising:
a first encoder;
a first decoder;
a second encoder in communication with the first encoder; and
a second decoder in communication with the first decoder.
3. The controller of claim 2 wherein the first encoder is adapted to perform a first ECC technique and the second encoder is adapted to perform a second ECC technique.
4. The controller of claim 3 wherein the first ECC technique is different from the second ECC technique.
5. The controller of claim 1 wherein the multi-level solid state non-volatile memory array comprises one or more flash EEPROM arrays.
6. The controller of claim 1 wherein the output signal is generated based on soft information.
7. A method of operating a controller for a multi-level solid state non-volatile memory array having memory cells, the memory cells adapted to store data using a first number of digital levels, the method comprising:
encoding a series of data bits to generate a series of encoded data bits;
converting the series of encoded data bits into a series of data symbols;
sending, to the memory array, a stored series of data symbols based on the series of data symbols for storage in a memory cell of the multi-level solid state non-volatile memory array;
generating an output signal based on data associated with the stored series of data symbols, the output signal characterized by a second number of digital levels greater than the first number of digital levels used to store the series of data symbols in the memory cell; and
outputting a series of output data symbols based on the output signal.
8. The method of claim 7 further comprising:
encoding data bits to generate the series of data bits; and
decoding the series of output data symbols.
9. The method of claim 8 wherein the encoding of the data bits is performed in accordance with a first ECC technique and the encoding of the series of data bits is performed in accordance with a second ECC technique.
10. The method of claim 9 wherein the first ECC technique is different from the second ECC technique.
11. The method of claim 7 wherein the multi-level solid state non-volatile memory array comprises one or more flash EEPROM arrays.
12. The method of claim 7 wherein the output signal comprises soft information.
13. A controller for a multi-level solid state non-volatile memory array having memory cells, the memory cells adapted to store data using a first number of digital levels, the controller comprising:
means for encoding a series of data bits to generate a series of encoded data bits;
means for converting the series of encoded data bits into a series of data symbols;
means for sending, to the memory array, a stored series of data symbols based on the series of data symbols for storage in a memory cell of the multi-level solid state non-volatile memory array;
means for generating an output signal based on data associated with the stored series of data symbols, the output signal characterized by a second number of digital levels greater than the first number of digital levels used to store the series of data symbols in the memory cell; and
means for outputting a series of output data symbols based on the output signal.
14. The controller of claim 13 further comprising:
means for encoding data bits to generate the series of data bits; and
means for decoding the series of output data symbols.
15. The controller of claim 14 wherein the encoding of the data bits is performed in accordance with a first ECC technique and the encoding of the series of data bits is performed in accordance with a second ECC technique.
16. The controller of claim 15 wherein the first ECC technique is different from the second ECC technique.
17. The controller of claim 13 wherein the multi-level solid state non-volatile memory array comprises one or more flash EEPROM arrays.
18. The controller of claim 13 wherein the output signal comprises soft information.