Method and system for monitoring module power information in a communication device
View Patent ↗A method for communication is disclosed and includes, in a single chip including a plurality of on-chip devices, acquiring, from at least one of the plurality of on-chip devices, power information for the at least one of the plurality of on-chip devices. The acquiring may be in response to a query signal received by the at least one of the plurality of on-chip devices. An output signal indicative of power status of the at least one of the plurality of on-chip devices may be generated from within the chip, based on the acquired power information. The acquired power information may be communicated to the off-chip device. The acquired power information may be wirelessly communicated to the off-chip device via an antenna or an infrared transmitter on the single chip. The acquired power information may be communicated to an off-chip device via a wired connection on the single chip.
1. A method for communication, the method comprising:
in a single chip comprising a plurality of on-chip devices:
acquiring, at a respective power analyzer of a plurality of power analyzers, power information from a respective on-chip device of the plurality of on-chip devices, the acquiring in response to a query signal received by the respective power analyzer; and
generating from within the single chip, an output signal indicative of power status of each of the plurality of on-chip devices, based on the acquired power information, the output signal comprising a plurality of blocks of one or more active bits, each block of the plurality of blocks being indicative of power consumption of a respective on-chip device during one or more clock cycles.
2. The method according to claim 1 , further comprising communicating the output signal to an off-chip device.
3. The method according to claim 2 , further comprising wirelessly communicating the output signal to the off-chip device via an antenna or an infrared transmitter on the single chip.
4. The method according to claim 1 , further comprising communicating the output signal to an off-chip device via a wired connection on the single chip.
5. The method according to claim 1 , further comprising communicating the output signal to an off-chip device via a general purpose input/output (GPIO) connection on the single chip.
6. The method according to claim 1 , further comprising communicating the output signal to an off-chip device via a plurality of pin connections.
7. The method according to claim 1 , further comprising receiving the query signal from a wireless device that is external to the single chip.
8. The method according to claim 1 , wherein each of the plurality of on-chip devices comprises a wireless transceiver interface.
9. The method according to claim 1 , wherein the output signal comprises at least one of a clock signal or a data signal.
10. The method according to claim 9 , wherein the data signal comprises sequential power information for the plurality of on-chip devices.
11. The method according to claim 1 , further comprising receiving the query signal via a wireless device that is integrated within the single chip.
12. The method according to claim 1 , wherein the power information comprises power consumption.
13. A system for communication, the system comprising:
a single chip comprising a plurality of on-chip devices;
a plurality of device power analyzers configured to:
acquire power information from a respective one of the plurality of on-chip devices, the acquiring in response to a query signal received by the plurality of device power analyzers; and
a main power analyzer configured to generate an output signal indicative of power status of each of the plurality of on-chip devices based on the acquired power information, the output signal comprising a plurality of blocks of one or more active bits, each block of the plurality of blocks being indicative of power consumption of a respective on-chip device during one or more clock cycles.
14. The system according to claim 13 , wherein the main power analyzer is further configured to communicate the output signal to an off-chip device.
15. The system according to claim 14 , wherein the main power analyzer is further configured to wirelessly communicate the output signal to the off-chip device via an antenna or an infrared transmitter on the single chip.
16. The system according to claim 13 , wherein the main power analyzer is further configured to communicate the output signal to an off-chip device via a wired connection on the single chip.
17. The system according to claim 13 , wherein the main power analyzer is further configured to communicate the output signal to an off-chip device via a general purpose input/output (GPIO) connection on the single chip.
18. The system according to claim 13 , wherein the main power analyzer is further configured to communicate the output signal to an off-chip device via a plurality of pin connections.
19. The system according to claim 13 , wherein the plurality of device power analyzers are further configured to receive the query signal from a wireless device that is external to the single chip.
20. The system according to claim 13 , wherein each of the plurality of on-chip devices comprises a wireless transceiver interface.
21. The system according to claim 13 , wherein the output signal comprises at least one of a clock signal or a data signal.
22. The system according to claim 21 , wherein the data signal comprises sequential power information for the plurality of on-chip devices.
23. The system according to claim 13 , wherein the plurality of device power analyzers are further configured to receive the query signal via a wireless device that is integrated within the single chip.
24. The system according to claim 13 , wherein the power information comprises power consumption.