Memory mirroring with memory compression
View Patent ↗Systems and methods to manage memory are provided. A particular method may include storing data in a primary memory that is in communication with a processor and storing in a mirrored data in a mirrored memory. The mirrored data may be compressed, and the mirrored memory may be in communication with the processor. A failure condition associated with the data of the primary memory may be detected. In response to the detected failure condition, the mirrored data in the mirrored memory may be accessed.
1. A method of managing memory, the method comprising:
storing data in a primary memory in communication with a processor;
storing in a mirrored memory mirrored data that mirrors the data stored in the primary memory, wherein the mirrored data is compressed and wherein the mirrored memory is in communication with the processor;
detecting a failure condition associated with the primary memory;
in response to the detected failure condition, enabling the processor to access the mirrored data in the mirrored memory and disabling the processor from accessing the data in the primary memory, wherein enabling the processor to access the mirrored data in the mirrored memory and disabling the processor from accessing the data in the primary memory further comprises changing a virtual address associated with a physical address of the primary memory to a virtual address associated with a physical address of the mirrored memory; and
in response to a corrective action configured to resolve the failure condition, enabling the processor to access the data in the primary memory and disabling the processor from accessing the mirrored data in the mirror memory.
2. The method of claim 1 , further comprising determining whether to access the mirrored memory based on a type of the failure condition, a frequency of the failure condition, or both.
3. The method of claim 1 , further comprising using at least one of the processor, a hypervisor, or an operating system to switch from enabling the processor to access the data in the primary memory to enabling the processor to access the mirrored data in the mirrored memory.
4. The method of claim 1 , further comprising compressing the mirrored data using a compression ratio of about four to one.
5. The method of claim 1 , further comprising using at least one of the processor, a hypervisor, or an operating system to detect the failure condition.
6. The method of claim 1 , further comprising housing the mirrored memory and the primary memory on a common circuit board.
7. The method of claim 1 , further comprising limiting a data capacity of the primary memory based on a capacity of the mirrored memory.
8. The method of claim 1 , wherein the mirrored memory further stores second mirrored data that mirrors second data stored in a second primary memory.
9. The method of claim 1 , further comprising storing in a second mirrored memory second mirrored data that mirrors the data stored in the primary memory.
10. An apparatus, comprising:
a primary memory configured to store data, wherein the data is uncompressed;
a mirrored memory configured to store mirrored data including a copy of the data, wherein the mirrored data is compressed; and
a processor in communication with the primary memory and the mirrored memory, wherein the processor is configured to:
detect a failure condition associated with the primary memory; and
in response to the detected failure condition, access the mirrored data in the mirrored memory, wherein accessing the mirrored data in the mirrored memory includes disabling the processor from accessing the data in the primary memory by changing a virtual address associated with a physical address of the primary memory to a virtual address associated with a physical address of the mirrored memory.
11. The apparatus of claim 10 , wherein the failure condition includes a detected error.
12. The apparatus of claim 10 , wherein the processor is directly coupled to the primary memory.
13. The apparatus of claim 10 , further comprising a buffer coupled in between the processor and the primary memory, the mirrored memory, or both.
14. The apparatus of claim 10 , further comprising a memory controller coupled in between the processor and the primary memory, the mirrored memory, or both.
15. The apparatus of claim 10 , wherein the mirrored memory and the primary memory are housed on a common circuit board.
16. The apparatus of claim 10 , wherein the processor is configured to limit a data capacity of the primary memory based on a capacity of the mirrored memory.
17. The apparatus of claim 10 , wherein the mirrored memory occupies a smaller space than the primary memory on a circuit board.
18. A computer-readable storage device storing instructions that, when executed by a computer, cause the computer to perform operations comprising:
detecting a failure condition associated with a primary memory;
in response to the detected failure condition, enabling a processor to access mirrored data in a mirrored memory and disabling the processor from accessing the data in the primary memory, the mirrored data including a copy of the data, wherein enabling the processor to access the mirrored data in the mirrored memory and disabling the processor from accessing the data in the primary memory includes changing a virtual address associated with a physical address of the primary memory to a virtual address associated with a physical address of the mirrored memory; and
in response to a corrective action configured to resolve the failure condition, enabling the processor to access the data in the primary memory and disabling the processor from accessing the mirrored data in the mirrored memory.