On-the-fly permutation of vector elements for executing successive elemental instructions
A device system and method for processing program instructions, for example, to execute intra vector operations. A fetch unit may receive a program instruction defining different operations on data elements stored at the same vector memory address. A processor may include different types of execution units each executing a different one of a predetermined plurality of elemental instructions. Each program instruction may be a combination of one or more of the elemental instructions. The processor may receive a vector of data elements stored non-consecutively at the same vector memory address to be processed by a same one of the elemental instructions and a vector of configuration values independently associated with executing the same elemental instruction on the non-consecutive data elements. At least two configuration values may be different to implement different operations by executing the same elemental instruction using the different configuration values on the vector of non-consecutive data elements.
1. A method comprising:
at a first stage:
loading, from a data memory into a configuration vector memory within a processor configuration values, pointers to non-consecutive elements of data elements, stored at a source vector memory within the processor to be used for executing a program instruction;
wherein the program instruction is a combination of two or more of predetermined elemental instructions, each elemental instruction executable at a different type of execution unit within the processor; and
at a second stage:
executing the elemental instructions of the program instruction in successive operations, wherein executing a first elemental instruction comprises:
using a first portion of the configuration values stored at the configuration vector memory to permute on-the-fly data elements in the source vector memory such that non-consecutive data elements are input to a first-type execution unit;
executing the first elemental instruction in the first-type execution unit according to the first portion of the configuration values; and
outputting the result of the first-type execution unit to a first-result vector memory, which serves as a source vector register for a second-type execution unit which executes a second successive elemental instruction;
executing the second elemental instruction in the second-type execution unit according to a second portion of the configuration values stored at a second configuration vector memory and values stored at the first-result vector memory; and
outputting the result of the second-type execution unit to a second-result vector memory,
wherein each type of execution unit comprises parallel execution units to execute the corresponding elemental instruction in parallel.
2. The method of claim 1 further comprising:
executing a third elemental instruction in a third-type execution unit according to a third portion of the configuration values stored at a third configuration vector memory and values stored at the second-result vector memory, which serves as a source vector register for the third-type execution unit; and
outputting the result of the third-type execution unit to a third-result vector memory.
3. The method of claim 1 , wherein the predetermined elemental instructions comprise multiplication/division, addition/subtraction, sign change/conjugation and accumulation of a previous result.
4. The method of claim 1 , comprising simultaneously executing the first elemental instruction on the plurality of non-consecutive data elements retrieved in the single retrieve operation.
5. A system comprising:
a data memory; and
a processor connected to the data memory via a data memory bus, wherein the processor comprises a source vector memory and different types of execution units, each configured to execute a respective elemental instruction,
wherein a configuration vector memory within the processor is configured to receive from the data memory, configuration values including pointers to non-consecutive elements of data elements stored at the source vector memory to be used for executing a program instruction, which is a combination of two or more of predetermined elemental instructions, each executable at one of the execution units,
wherein the processor is configured to execute elemental instructions of the program instruction in successive operations, wherein executing a first elemental instruction comprises:
using a first portion of the configuration values stored at the configuration vector memory to permute on-the-fly data elements in the source vector memory such that non-consecutive data elements are input to a first-type execution unit;
executing the first elemental instruction in the first-type execution unit according to the first portion of the configuration values; and
outputting the result of the first-type execution unit to a first-result vector memory, which serves as a source vector register for a second-type execution unit which executes a successive elemental instruction,
and executing the second elemental instruction in the second-type execution unit using a second portion of the configuration values stored at a second configuration vector memory and values stored at the first-result vector memory and outputting the result of the second-type execution unit to a second-result vector memory,
wherein each type of execution unit comprises parallel execution units to execute the corresponding elemental instruction in parallel.
6. The system of claim 5 , wherein each of the parallel execution units of the same type executes the same elemental instruction using a single instruction multiple data (SIMD) architecture.