IP Library Granted Patent US 8,415,837
Granted Patent B2
US 8,415,837 · App. 12/949,343 · Granted Apr 9, 2013

Switch mode voltage rectifier, RF energy conversion and wireless power supplies

Inventors: Paul Theilmann (San Diego, CA); Peter Asbeck (Del Mar, CA)
Assignee: The Regents of the University of California
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Quick Facts
Patent No.
US 8,415,837
App. No.
12/949,343
Granted
Apr 9, 2013
Kind
B2
Abstract

Embodiments of the present invention provide cross-coupled rectifiers that use near zero-threshold transistors in a switching topology, but provide a topology that avoids reverse conduction problems. Importantly, preferred embodiment rectifiers of the invention only provide a slightly increased on-resistance in each branch, while providing both very high operating efficiency and very low turn-on voltage. An embodiment of the invention is a voltage rectifier for the conversion of RF energy into DC voltage with a turn-on threshold voltages approaching 0V.

Claims (30)

1. A very lower power RF voltage rectifier, comprising:

differential positive and negative inputs;

a load; and

a switching mode CMOS gate cross-connected bridge connecting said differential input to said load, said CMOS gate cross-connected bridge comprising,

a first series path from the positive input through a first near zero threshold PMOS switching transistor and first near zero-threshold NMOS blocking transistor to one of ground or a load;

a second series path from the negative input through a first near zero-threshold NMOS switching transistor and second near zero-threshold PMOS blocking transistor to the other of said load and said ground;

a third series path from between the negative input through a third near zero-threshold PMOS switching transistor and a third near zero-threshold NMOS blocking transistor to said one of ground or a load; and

a fourth series path from the positive input through a fourth near zero-threshold NMOS switching transistor and fourth near zero-threshold PMOS blocking transistor to the other of said load and said ground.

2. The rectifier of claim 1 , wherein said differential positive and negative inputs are connected to an RF antenna.

3. The rectifier of claim 2 , wherein said load comprises a DC biomedical device.

4. The rectifier of claim 2 , wherein said load comprises a DC RFID circuit.

5. A multi-stage rectifier comprises a series of rectifiers of claim 1 capacitively coupled between said inputs and said load.

6. The rectifier of claim 1 , wherein said switching and blocking transistors comprise silicon on insulator near zero-threshold transistors.

7. The rectifier of claim 6 , wherein said switching and blocking transistors comprise silicon on sapphire near zero-threshold transistors.

8. The rectifier of claim 1 , wherein said switching and blocking transistors comprise triple well near zero-threshold transistors.

9. The rectifier of claim 1 , wherein said switching and blocking transistors comprise programmable threshold near zero-threshold transistors.

10. The rectifier of claim 1 , wherein the widths of NMOS and PMOS transistors in said CMOS cross-connected bride is set for equal on-resistance.

11. A very lower power RF voltage rectifier, comprising:

a CMOS gate cross-connected switching mode bridge having near zero-threshold devices to convert RF signals to DC energy; and

blocking transistor means for blocking shoot through current losses.

12. A very lower power RF voltage rectifier, comprising:

a differential input connected to a gate of a first near zero-threshold PMOS switching transistor, a gate of a second near zero-threshold NMOS switching transistor, a gate of a third near-zero threshold NMOS blocking transistor, a source of a third near-zero threshold PMOS switching transistor, a gate of a fourth near zero-threshold PMOS blocking transistor, and a source of a fourth near zero-threshold NMOS switching transistor;

an opposite differential input connect to a source of said first near zero-threshold PMOS switching transistor, a gate of a first near-zero threshold NMOS blocking transistor, a source of said second near zero-threshold NMOS switching transistor, a gate of a second near-zero threshold PMOS blocking transistor, a gate of said third near zero-threshold PMOS switching transistor, and a gate of said fourth near zero-threshold NMOS switching transistor;

sources of said first and third blocking transistors being connected to each other or to each other and a load;

sources of said second and further blocking transistors being connected to each other or to each other and a load; and

drains of respective ones of said first through fourth switching transistors being connect to drains of said first through further blocking transistors.

13. The rectifier of claim 12 , wherein said switching and blocking transistors comprise silicon on insulator near zero-threshold transistors.

14. The rectifier of claim 13 , wherein said switching and blocking transistors comprise silicon on sapphire near zero-threshold transistors.

15. The rectifier of claim 12 , wherein said switching and blocking transistors comprise triple well near zero-threshold transistors.

16. The rectifier of claim 12 , wherein said switching and blocking transistors comprise programmable threshold near zero-threshold transistors.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 3, 2011
From: THEILMANN, PAUL; ASBECK, PETER
To: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
Reel/Frame 025739/0180 →
Continuity (2)
Provisional Application 61262282 · Nov 18, 2009
Related Publication 20110124310A1 · May 26, 2011