Semiconductor memory device
View Patent ↗A dummy cell array is provided in a memory cell array, and an intermediate buffer is provided between input/output circuits, whereby control signals to the input/output circuits can be operated at high speed and with a high frequency while the area increasing effect is reduced even in a memory with a large bit width.
1. A semiconductor memory device including:
a memory cell array including memory cells configured to store data and arranged in an array;
a first circuit configured to have at least one of a function of outputting data from the memory cells and a function of inputting data to the memory cells; and
a second circuit configured to have at least one of a function of outputting data from the memory cells and a function of inputting data to the memory cells,
wherein
at least one line of dummy cells other than the memory cells configured to store the data is provided in the memory cell array and arranged in parallel with a bit line direction of the memory cells, and
a buffer circuit configured to buffer a control signal to the first or second circuit is provided between the first and second circuits in a region extending in the bit line direction from the dummy cell line.
2. The semiconductor memory device of claim 1 , wherein
the dummy cells each have a substrate contact for the memory cell array.
3. The semiconductor memory device of claim 1 , wherein
the dummy cells each have the same shape as that of each of a portion of the memory cells.
4. The semiconductor memory device of claim 1 , wherein
a gate and a diffusion layer of each of the dummy cells have the same shape as that of each of the memory cells.
5. The semiconductor memory device of claim 1 , wherein
the dummy cells each include a first bit line, and the first bit line is connected to a precharge transistor having the same configuration as that of a precharge transistor configured to precharge a bit line possessed by the corresponding memory cell.
6. The semiconductor memory device of claim 1 , wherein
the dummy cells each include a first bit line, and the first bit line is set to a predetermined potential.
7. The semiconductor memory device of claim 1 , wherein
the dummy cells each include a first bit line and a second bit line, and the first bit line is set to a first potential, and the second bit line is set to a second potential.
8. The semiconductor memory device of claim 1 , wherein
the dummy cells each include at least one bit line, and at least one of one or more transistors connected to the at least one bit line is not connected to a word line configured to activate the memory cells.
9. The semiconductor memory device of claim 1 , wherein
the dummy cells each include a first bit line, and the first bit line is connected to the outside via a path different from a bit line of the memory cells.
10. The semiconductor memory device of claim 1 , wherein
the dummy cells are each a redundancy replacement cell for the memory cells.
11. The semiconductor memory device of claim 1 , wherein
an amplifier circuit configured to output data from the memory cells is activated based on data read out from the dummy cells.