IP Library Granted Patent US 8,144,747
Granted Patent B2
US 8,144,747 · App. 12/949,413 · Granted Mar 27, 2012

Primary and secondary synchronization codes from first, second, third sequences

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Quick Facts
Patent No.
US 8,144,747
App. No.
12/949,413
Granted
Mar 27, 2012
Kind
B2
Abstract

A wireless communication system. The system comprises transmitter circuitry (BST 1 ), the transmitter circuitry comprising encoder circuitry ( 50 ) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a secondary synchronization code (SSC). The encoder circuitry comprises of circuitry ( 50 1 ) for providing the primary synchronization code in response to a first sequence ( 32 ). The encoder circuitry further comprises circuitry ( 50 2 ) for providing the secondary synchronization code in response to a second sequence ( 54 ) and a third sequence ( 56 ). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences in the plurality of sequences. The third sequence comprises a subset of bits from the first sequence.

Claims (10)

1. A method of forming synchronization codes for a wireless communication device, comprising:

A. providing a primary synchronization code in response to a first sequence; and

B. providing a secondary synchronization code in response to a second sequence and a third sequence, the third sequence being different from the first sequence;

i. the second sequence is selected from a plurality of sequences, each of the plurality of sequences is orthogonal with respect to all other sequences in the plurality of sequences;

ii. the second sequence includes a plurality of code words and each of the plurality of code words is selected from a plurality of Hadamard sequences;

iii. the second sequence consists of fifteen of the code words; and

iv. the third sequence includes a sequence of bits from the first sequence, the sequence of bits from the first sequence is repeated a plurality of times in the third sequence; and

C. outputting the primary synchronization code and the secondary synchronization code from synchronization code generator circuitry.

2. The method of claim 1 , wherein the first sequence includes a hierarchical sequence.

3. The method of claim 1 , in which the first sequence includes a Golay sequence.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 14, 2020
From: INTEL CORPORATION
To: APPLE INC.
Reel/Frame 052414/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2017
From: TEXAS INSTRUMENTS INCORPORATED
To: INTEL CORPORATION
Reel/Frame 041383/0040 →