IP Library Granted Patent US 8,193,060
Granted Patent B2
US 8,193,060 · App. 12/949,434 · Granted Jun 5, 2012

Method of manufacturing a semiconductor device

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Quick Facts
Patent No.
US 8,193,060
App. No.
12/949,434
Granted
Jun 5, 2012
Kind
B2
Abstract

Provided is a method for manufacturing a semiconductor device. A well region formed on a semiconductor substrate includes a plurality of trench regions, and a source electrode is connected to a source region formed on a substrate surface between the trench regions. Adjacently to the source region, a high concentration region is formed, which is brought into butting contact with the source electrode together with the source region, whereby a substrate potential is fixed. A drain region is formed at a bottom portion of the trench region, whose potential is taken to the substrate surface by a drain electrode buried inside the trench region. An arbitrary voltage is applied to a gate electrode, and the drain electrode, whereby carriers flow from the source region to the drain region and the semiconductor device is in an on-state.

Claims (25)

1. A method of manufacturing a semiconductor device, comprising:

forming a first conductivity type well region above a semiconductor substrate;

forming a plurality of trench regions at a depth smaller than a depth of the first conductivity type well region;

forming a gate insulating film;

forming a gate electrode film;

removing, by anisotropic etching, the gate insulating film and the gate electrode film formed on a bottom portion of each of the plurality of trench regions and a part of the gate insulating film and the gate electrode film formed on a surface of the semiconductor substrate between two of the plurality of trench regions;

forming a second conductivity type drain region at a part of a bottom of each of the plurality of trench regions such that a width of the drain region is less than a width of the trench region;

forming an interlayer insulating film;

removing, by etching, a part of the interlayer insulating film formed on the gate electrode film, a part of the interlayer insulating film formed on the bottom portion of each of the plurality of trench regions, and a part of the interlayer insulating film formed on the surface of the semiconductor substrate between two of the plurality of trench regions;

forming a metal film; and

etching a part of the metal film.

2. A method of manufacturing a semiconductor device according to claim 1 , wherein second conductivity type drain region is formed such that lateral sides of the drain region are apart from corresponding sides of the trench region by at least a thickness of the gate insulating film.

3. A method of manufacturing a semiconductor device according to claim 2 , further comprising forming, before the forming the first conductivity type well region on the semiconductor substrate, a second conductivity type low concentration diffusion region on the semiconductor substrate, wherein the second conductivity type drain region is formed within the second conductivity type low concentration diffusion region such that the second conductivity type low concentration diffusion region surrounds the second conductivity type drain region.

4. A method of manufacturing a semiconductor device, comprising:

forming a first conductivity type low concentration diffusion region on a semiconductor substrate;

forming a second conductivity type well region on the first conductivity type low concentration diffusion region such that the first conductivity type low concentration diffusion region is between the semiconductor substrate and the second conductivity type well region;

forming a plurality of trench regions at a depth smaller than a depth of the second conductivity type well region;

forming a gate insulating film;

forming a gate electrode film;

removing, by anisotropic etching, the gate insulating film and the gate electrode film formed on a bottom portion of each of the plurality of trench regions and a part of the gate insulating film and the gate electrode film formed on a surface of the semiconductor substrate between two of the plurality of trench regions;

forming an interlayer insulating film;

removing, by etching, a part of the interlayer insulating film formed on the gate electrode film, a part of the interlayer insulating film formed on the bottom portion of each of the plurality of trench regions, and a part of the interlayer insulating film formed on the surface of the semiconductor substrate between two of the plurality of trench regions;

forming a metal film; and

etching a part of the metal film.

5. A method of manufacturing a semiconductor device according to claim 4 , wherein the forming the first conductivity type low concentration diffusion region on the entire surface of the region on which the transistor is formed comprises an epitaxial growth.

Assignments (4)
CHANGE OF ADDRESS Recorded Jun 8, 2023
From: ABLIC INC.
To: ABLIC INC.
Reel/Frame 064021/0575 →
CHANGE OF NAME Recorded Mar 12, 2018
From: SII SEMICONDUCTOR CORPORATION
To: ABLIC INC.
Reel/Frame 045567/0927 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 037783 FRAME: 0166. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Feb 23, 2016
From: SEIKO INSTRUMENTS INC
To: SII SEMICONDUCTOR CORPORATION
Reel/Frame 037903/0928 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 11, 2016
From: SEIKO INSTRUMENTS INC
To: SII SEMICONDUCTOR CORPORATION .
Reel/Frame 037783/0166 →