Duty cycle translator methods and apparatus
View Patent ↗Methods and apparatus for translating duty cycle information in duty-cycle-modulated signals to higher frequencies or higher data rates. An exemplary duty cycle translator includes a duty cycle evaluator, a high-speed digital counter, and a comparator. The duty cycle evaluator generates a first digital number representing a duty cycle of a low-frequency input duty-cycle-modulated (DCM) signal. The comparator compares the first digital number to a second digital number generated by the high-speed digital counter, and generates, based on the comparison, an output DCM signal having a higher frequency or data rate than the frequency or data rate of the low-frequency input DCM signal but a duty cycle that is substantially the same as the duty cycle of the low-frequency input DCM signal.
1. A duty cycle translator, comprising:
a duty cycle evaluator configured to receive an input duty-cycle-modulated (DCM) signal and generate a first digital number representing a duty cycle of the input DCM signal;
a first digital counter configured to generate a second digital number; and
a comparator configured to compare the first and second digital numbers and generate an output DCM signal having a higher frequency or higher data rate than a frequency or data rate of the input DCM signal and a duty cycle that is substantially the same as a duty cycle of the input DCM signal
wherein said duty cycle evaluator comprises:
a second digital counter configured to generate a count representing a portion of a period of the input DCM signal during which the input DCM signal is high;
a third digital counter configured to generate a count representing a period of the input DCM signal; and
a divider configured to divide the count from said second digital counter by the count from said third digital counter to generate said first digital number.
2. A method of translating duty cycle information in a duty-cycle-modulated (DCM) to a higher frequency or data rate, comprising:
receiving an input DCM signal;
generating a first digital number representing a duty cycle of the input DCM signal at a first rate;
generating a second digital number at a second rate higher than said first rate; and
comparing the first and second digital numbers to form an output DCM signal having a higher frequency or data rate than a frequency or data rate of the input DCM signal and a duty cycle that is substantially the same as a duty cycle of the input DCM signal,
wherein generating the first digital number at the first rate comprises:
generating a first count representing a portion of a period of the input DCM signal during which the input DCM signal is high;
generating a second count representing a period of the input DCM signal; and
dividing said first count by said second count to generate said first digital number.