IP Library Granted Patent US 8,252,639
Granted Patent B2
US 8,252,639 · App. 12/951,981 · Granted Aug 28, 2012

Thin film transistor array panel and method for manufacturing the same

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Quick Facts
Patent No.
US 8,252,639
App. No.
12/951,981
Granted
Aug 28, 2012
Kind
B2
Abstract

The present invention provides a thin film transistor array panel comprising: an insulating substrate; a gate line formed on the insulating substrate and having a gate electrode; a gate insulating layer formed on the gate line; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; diffusion barriers formed on the semiconductor and containing nitrogen; a data line crossing the gate line and having a source electrode partially contacting the diffusion barriers; a drain electrode partially contacting the diffusion barriers and facing the source electrode on the gate electrode; and a pixel electrode electrically connected to the drain electrode.

Claims (12)

1. A manufacturing method of a thin film transistor array panel, comprising:

forming a gate line on an insulating substrate;

depositing a gate insulating layer and a first a-Si layer in sequence;

depositing a second a-Si layer doped with a conductive impurity on the first a-Si layer and a third a-Si layer including nitrogen on the second a-Si layer;

patterning the third a-Si layer, the second a-Si layer, and the first a-Si layer to form a pre-diffusion barrier, pre-ohmic contacts, and a semiconductor layer, respectively;

forming a data line and a drain electrode partially overlapping the pre-diffusion barrier;

etching the pre-diffusion barrier and the pre-ohmic contacts disposed between the data line and the drain electrode to form diffusion barriers and ohmic contacts, respectively; and

forming a pixel electrode electrically connected to the drain electrode.

2. The method of claim 1 , wherein the data line and the drain electrode comprise first to third conductor layers, the first and third conductor layers comprising Mo or a Mo alloy, and the second layer comprising Al or an Al alloy.

3. The method of claim 1 , wherein the third a-Si layer is deposited in a same environment as the second a-Si layer except that the third a-Si layer is deposited in an environment that includes a gas containing nitrogen.

4. The method of claim 3 , wherein the gas containing nitrogen is one of N 2 , NH 3 , and a mixture of N 2 and NH 3 .

5. The method of claim 1 , further comprising forming color filters before forming the pixel electrode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 22, 2012
From: SAMSUNG ELECTRONICS CO., LTD.
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 029007/0959 →