Display substrate and method for manufacturing the same
View Patent ↗A method of forming a display substrate includes forming an array layer on a substrate, forming a passivation layer on the array layer, forming a photoresist pattern on the passivation layer corresponding to a gate line, a source line and a thin-film transistor of the array layer, etching the passivation layer using the photoresist pattern as a mask, Non-uniformly surface treating a surface of the photoresist pattern, forming a transparent electrode layer on the substrate having the surface-treated photoresist pattern formed thereon and forming a pixel electrode. The forming a pixel electrode includes removing the photoresist pattern and the transparent electrode layer, such as by infiltrating a strip solution into the surface-treated photoresist pattern.
1. A display substrate comprising:
a first metal pattern including a first metal layer and a second metal layer forming a gate line extended to a first direction, a gate end portion pattern, and a gate electrode of a thin-film transistor (“TFT”);
a second metal pattern including a source line, a source electrode, and a drain electrode of the TFT, the source line being extended to a second direction substantially perpendicular to the first direction;
a passivation layer on the gate line, the source line and the TFT;
a first via hole exposing a side surface of the first metal layer of the gate end portion pattern;
a first electrode contacting the side surface of the first metal layer of the gate end portion pattern; and
a pixel electrode which contacts an end side surface of the drain electrode in a plan view, the pixel electrode overlapping with a portion of the passivation layer on the drain electrode, the portion being extended from the end side surface of the drain electrode.
2. The display substrate of claim 1 , further comprising a plurality of gate lines,
wherein the first metal pattern further includes a storage common line extended substantially parallel with the gate lines and disposed between adjacent gate lines.
3. The display substrate of claim 1 , further comprising a channel layer formed under the second metal pattern.
4. The display substrate of claim 1 , wherein the pixel electrode comprises amorphous indium tin oxide (“a-ITO”).
5. The display substrate of claim 1 , wherein the pixel electrode contacts an outer side surface of the passivation layer.
6. The display substrate of claim 3 , wherein the pixel electrode contacts an outer side surface of the channel layer under the second metal pattern.
7. The display substrate of claim 1 , wherein
the first metal layer, the second metal pattern, the passivation layer and the pixel electrode are on a base substrate, and
the pixel electrode contacts the base substrate.