Class AB output stages and amplifiers including class AB output stages

1. A buffer stage, comprising:

a flipped voltage follower connected between a high voltage rail and a low voltage rail and including an input and an output;

an emitter follower connected between the high voltage rail and the low voltage rail and including an input and an output; and

a resistor connecting the output of the flipped voltage follower to the output of the emitter follower;

wherein the input of the flipped voltage follower and the input of the emitter follower are connected together and provide an input of the buffer stage; and

wherein the output of the emitter follower provides an output of the buffer stage.

2. The buffer stage of claim 1 , wherein the resistor equalizes output impedances of the flipped voltage follower and the emitter follower and causes outputs of the flipped voltage follower and the emitter follower to be summed at the output of the buffer stage.

3. The buffer stage of claim 1 , wherein:

the flipped voltage follower and the emitter follower each comprise bipolar junction transistors of the same type, but neither comprise bipolar junction transistors of the opposite type.

4. The buffer stage of claim 3 , wherein:

the flipped voltage follower and the emitter follower each comprise NPN transistors, but neither comprise PNP transistors.

5. The buffer stage of claim 3 , wherein:

the flipped voltage follower and the emitter follower each comprise PNP transistors, but neither comprise NPN transistors.

6. The buffer stage of claim 1 , further comprising:

a bias generator configured to bias at least one transistor of the flipped voltage follower and at least one transistor of the emitter follower.

7. The buffer stage of claim 6 , wherein the bias generator comprises a DC level shifter.

8. The buffer stage of claim 1 , wherein the flipped voltage follower comprises:

a first transistor (Q 5 ) having a base that provides the input of the flipped voltage follower, a collector connected by a first resistor (R 9 ) to a high voltage rail (Vcc), and an emitter that provides the output of the flipped voltage follower; and

a second transistor (Q 4 ) having a base, a collector connected to the emitter of the first transistor (Q 5 ), and an emitter connected to a low voltage rail (Vee).

9. The buffer stage of claim 8 , wherein the flipped voltage follower further comprises:

a capacitor (C 19 ) connected between the collector of the first transistor (Q 5 ) and the base of the second transistor (Q 4 ).

10. The buffer stage of claim 9 , further comprising:

a bias generator configured to bias the base of the second transistor (Q 4 ).

11. The buffer stage of claim 9 , wherein the emitter follower comprises:

a third transistor (Q 32 ) having a base that provides the input of the emitter follower, a collector connected to the high voltage rail (Vcc), and an emitter that provides the output of the emitter follower; and

a fourth transistor (Q 43 ) having a base connected to the base of the second transistor (Q 4 ), a collector connected to the emitter the third transistor (Q 32 ), and having an emitter connected to the low voltage rail (Vee).

12. The buffer stage of claim 11 , further comprising:

a bias generator configured to bias the base of the second transistor (Q 4 ) and the base of the fourth transistor (Q 43 ).

13. The buffer stage of claim 1 , wherein the buffer stage operates as a class AB unity gain amplifier.

14. A differential buffer stage, comprising:

a first buffer that accepts a first input signal; and

a second buffer that accepts a second input signal;

wherein each of the first and second buffers includes

a flipped voltage follower, including an input and an input, and connected between a high voltage rail and a low voltage rail;

an emitter follower, including an input and an output, and connected between the high voltage rail and the low voltage rail; and

a resistor connecting the output of the flipped voltage follower to the output of the emitter follower;

wherein the input of the flipped voltage follower and the input of the emitter follower are connected together and provide an input of the buffer stage; and

wherein the output of the emitter follower provides an output of the buffer stage.

15. The differential buffer stage of claim 14 , wherein:

the flipped voltage follower and the emitter follower of the first buffer, and the flipped voltage follower and the emitter follower of the second buffer, each comprise bipolar junction transistors of the same type, but neither comprise bipolar junction transistors of the opposite type.

16. The differential buffer stage of claim 14 , wherein:

the first buffer also includes a bias generator configured to bias at least one transistor of the flipped voltage follower and at least one transistor of the emitter follower of the first buffer; and

the second buffer also includes a bias generator configured to bias at least one transistor of the flipped voltage follower and at least one transistor of the emitter follower of the second buffer.

17. A fully differential operational amplifier, comprising:

a transconductance stage that provides differential inputs for the operation amplifier;

a differential output buffer stage including first and second buffers that provide differential outputs for the operation amplifier; and

wherein each of the first and second buffers of the differential output buffer stage includes

a flipped voltage follower, including an input and an input, and connected between a high voltage rail and a low voltage rail;

an emitter follower, including an input and an output, and connected between the high voltage rail and the low voltage rail; and

a resistor connecting the output of the flipped voltage follower to the output of the emitter follower;

wherein the input of the flipped voltage follower and the input of the emitter follower are connected together and provide an input of the buffer stage; and

wherein the output of the emitter follower provides an output of the buffer stage.

18. The fully differential operational amplifier of claim 17 , further comprising a voltage gain stage between the transconductance stage and the differential output buffer.

19. The differential buffer stage of claim 15 , wherein:

the flipped voltage follower and the emitter follower of the first buffer, and the flipped voltage follower and the emitter follower of the second buffer, each comprise NPN transistors, but neither comprise PNP transistors.

20. The differential buffer stage of claim 15 , wherein:

the flipped voltage follower and the emitter follower of the first buffer, and the flipped voltage follower and the emitter follower of the second buffer, each comprise PNP transistors, but neither comprise NPN transistors.

21. The fully differential operational amplifier of claim 17 , wherein:

the flipped voltage follower and the emitter follower of the first buffer, and the flipped voltage follower and the emitter follower of the second buffer, each comprise NPN transistors, but neither comprise PNP transistors.

22. The fully differential operational amplifier of claim 17 , wherein:

the flipped voltage follower and the emitter follower of the first buffer, and the flipped voltage follower and the emitter follower of the second buffer, each comprise PNP transistors, but neither comprise NPN transistors.