Semiconductor memory circuit equipped with multiplexer for reducing coupling capacitance of non-selected main bit lines
View Patent ↗A semiconductor memory circuit includes a memory cell array having a plurality of memory cells arranged in a row direction and a column direction; a row selecting unit for selecting the memory cells of the memory cell array aligned in the row direction; a column selecting unit for selecting the memory cells of the memory cell array aligned in the column direction; a plurality of main bit lines for outputting data of the memory cells; a data reading unit for reading data of one of the memory cells selected with the row selecting unit and the column selecting unit; a first multiplexer for connecting one of the main bit lines connected to the memory cell to the data reading unit; and a second multiplexer for connecting an adjacent main bit line situated adjacently outside the main bit line to a charging/discharging voltage source for setting at a specific voltage.
1. A semiconductor memory circuit, comprising:
a memory cell array having a plurality of memory cells arranged in a row direction and a column direction;
a row selecting unit for selecting the memory cells of the memory cell array aligned in the row direction;
a column selecting unit for selecting the memory cells of the memory cell array aligned in the column direction;
a plurality of main bit lines for outputting data of the memory cells;
a data reading unit for reading data of at least one of the memory cells selected with the row selecting unit and the column selecting unit;
a first multiplexer for connecting at least one of the main bit lines connected to the one of the memory cells to the data reading unit; and
a second multiplexer for connecting an adjacent main bit line situated adjacently outside the one of the main bit lines to a charging/discharging voltage source for setting at a specific voltage,
wherein said data reading unit includes a first sense amplifier and a second sense amplifier, said row selecting unit being arranged to select a pair of the memory cells connected to a pair of the main bit lines arranged adjacently, said first multiplexer being arranged to connect the pair of the main bit lines to the first sense amplifier and the second sense amplifier, respectively.
2. The semiconductor memory circuit according to claim 1 , wherein said second multiplexer is arranged to connect the main bit lines situated outside the pair of the main bit lines to the charging/discharging voltage source.
3. The semiconductor memory circuit according to claim 1 , wherein said second multiplexer is arranged to connect the adjacent main bit lines situated adjacently outside each of the pair of the main bit lines to the charging/discharging voltage source.
4. The semiconductor memory circuit according to claim 1 , wherein said second multiplexer is formed of a circuit the same as that of the first multiplexer.
5. The semiconductor memory circuit according to claim 1 , wherein said memory cell array includes a multi bit type memory cell.
6. The semiconductor memory circuit according to claim 1 , wherein said memory cell includes a transistor having a gate, a pair of diffusion layers as a source or a drain, said row selecting unit including a word line connected to the gate.
7. The semiconductor memory circuit according to claim 6 , wherein said row selecting unit includes a first sub bit line for connecting one of the diffusion layers to a common voltage source, a first transistor disposed between the common voltage source and the first sub bit line, a second sub bit line for connecting the other of the diffusion layers to the main bit line, and a second transistor disposed between the main bit line and the second sub bit line.