Comparator circuit

1. An analog-to-digital converter comprising:

a comparator configured to receive a first input signal and a second input signal;

in which at least one of said input signals is received between a drain terminal of a first transistor device and a source terminal of a second transistor device.

2. The converter of claim 1 , in which said comparator comprises an output comprising a level-shifting amplifier.

3. The converter of claim 1 , further comprising a cross-coupled regenerative load.

4. The converter of claim 1 , in which said comparator comprises a reset circuit for selectively resetting said comparator.

5. The converter of claim 1 , in which a DAC is connected to an input of said comparator.

6. The converter of claim 5 , in which an input to said DAC adjusts a trip point of said comparator.

7. The converter of claim 6 , in which said DAC adjusts said trip point by one of altering one of said input signals and altering a reference signal.

8. The converter of claim 1 , further comprising a reference signal source configured to produce a reference signal to be combined with at least one of said input signals before being compared by said comparator.

9. A method for comparing input signals performed by a comparator circuit, the method comprising:

receiving a first input signal between a drain terminal of a first transistor of said comparator circuit and a source terminal of a second transistor of said comparator circuit;

receiving a second input signal; and

outputting a value based on a comparison of said first input signal and said second input signal.

10. The method of claim 9 , in which receiving said second input signal comprises receiving said second input signal between a drain terminal of a third transistor of said comparator circuit and a source terminal of a fourth transistor of said comparator circuit.

11. The method of claim 9 , in which comparator circuit further comprises a cross-coupled regenerative load.

12. The method of claim 9 , further comprising selectively resetting said comparator circuit.

13. The method of claim 9 , in which a value of one of said first input signal and said second input signal is connected to a Digital-to-Analog Converter (DAC).

14. The converter of claim 13 , further comprising, adjusting a trip point of the comparator by changing an input to said DAC.

15. The converter of claim 13 , in which said DAC is configured to receive a differential signal.

16. The method of claim 9 , in which said transistors comprise one of CMOS transistors and bipolar junction transistors.

17. The method of claim 9 , further comprising combining said first input signal with a reference signal.

18. An Analog-to-Digital Converter (ADC) comprising:

a comparator configured to:

receive a first input signal between a drain terminal of a first transistor of said comparator circuit and a source terminal of a second transistor of said comparator circuit;

receive a second input signal; and

output a value based on a comparison of said first input signal and said second input signal.

19. The ADC of claim 18 , in which to receive said second input signal, said comparator is configured to receive said second input signal between a drain terminal of a third transistor of said comparator circuit and a source terminal of a fourth transistor of said comparator circuit.

20. The converter of claim 18 , in which said converter is further configured to combine said first input signal with a reference signal.

21. An analog-to-digital converter comprising:

a comparator comprising a first transistor device and a second transistor device, wherein a drain terminal of said first transistor device is connected to a source terminal of said second transistor device; and

two input terminals configured to receive, respectively, a first input signal and a second input signal;

in which at least one of said input terminals is located on said connection between said drain terminal of said first transistor device and said source terminal of said second transistor device.