IP Library Granted Patent US 8,163,591
Granted Patent B2
US 8,163,591 · App. 12/956,975 · Granted Apr 24, 2012

Backside illuminated image sensor

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Quick Facts
Patent No.
US 8,163,591
App. No.
12/956,975
Granted
Apr 24, 2012
Kind
B2
Abstract

A backside illuminated image sensor includes a photodiode, formed below the top surface of a semiconductor substrate, for receiving light illuminated from the backside of the semiconductor substrate to generate photoelectric charges, a reflecting gate, formed on the photodiode over the front upper surface of the semiconductor substrate, for reflecting light illuminated from the backside of the substrate and receiving a bias to control a depletion region of the photodiode, and a transfer gate for transferring photoelectric charges from the photodiode to a sensing node of a pixel.

Claims (40)

1. A method comprising:

providing light at a backside of a substrate;

reflecting the provided light onto a front side of a depletion region to generate and store a photoelectric charge; and

applying a bias signal at the front side of the depletion region to control the size of the depletion region.

2. The method of claim 1 , wherein said applying a bias signal comprises applying the bias signal during an integration of the photoelectric charge.

3. The method of claim 1 , wherein said reflecting the provided light comprises reflecting the provided light using a reflecting gate.

4. The method of claim 3 , wherein the reflecting gate comprises a metal silicide layer.

5. The method of claim 1 , further comprising using a photodiode at the backside of the substrate to form the depletion region.

6. The method of claim 5 , wherein said using a photodiode at the backside of the substrate to form the depletion region comprises using a pinned photodiode.

7. The method of claim 1 , further comprising integrating the photoelectric charge in the depletion region after said applying a bias signal.

8. The method of claim 6 , further comprising transferring the photoelectric charge from the depletion region to a diffusion node.

9. The method of claim 1 , wherein said applying a bias signal comprises applying a bias signal that extends the depletion region to a region proximate the backside of the substrate.

10. The method of claim 9 , wherein said providing light at a backside of a substrate comprises providing short-wavelength light.

11. The method of claim 9 , wherein said providing light at a backside of a substrate comprises providing blue light.

12. A method for operating a pixel of an image sensor, the method comprising:

providing light at a backside of a substrate;

using a reflecting gate disposed proximate a front side of the substrate to reflect the provided light onto a depletion region of a photodiode to generate and store photoelectric charges, wherein the photodiode is formed proximate a front surface of the substrate;

receiving a bias signal at the reflecting gate to control the size of a depletion layer in the depletion region; and

integrating the photoelectric charges in the depletion region after said receiving a bias signal.

13. The method of claim 12 , wherein the bias signal comprises a negative bias voltage.

14. The method of claim 12 , further comprising forming the reflecting gate to include a metal silicide layer.

15. The method of claim 14 , wherein said receiving a bias signal comprises receiving a bias signal that extends the depletion region to a region proximate the backside of the substrate.

16. The method of claim 15 , wherein said providing light at a backside of a substrate comprises providing short-wavelength light.

17. The method of claim 16 , wherein said providing light at a backside of a substrate comprises providing blue light.

18. A method for forming a pixel of an image sensor, the method comprising:

forming a photodiode proximate a front surface of a substrate;

forming an insulation layer proximate on a back surface of the substrate;

forming a color filter on the insulation layer;

forming a microlens on the color filter;

forming a reflecting gate on the front surface of the substrate proximate the photodiode; and

forming an electrical connection between the reflecting gate and a bias voltage supply.

19. The method of claim 18 , wherein said forming a color filter comprises forming a color filter that passes short-wavelength light.

20. The method of claim 18 , wherein said forming a color filter comprises forming a color filter that passes blue light.

21. The method of claim 18 , wherein said forming an insulation layer comprises forming an insulation layer from an anti-reflective material.

22. The method of claim 21 , wherein said forming an insulation layer from an anti-reflective material comprises forming an insulation layer including a layer selected from the group consisting of an oxide layer, a nitride layer, and a stacked structure thereof.

23. The method of claim 21 , wherein said forming an insulation layer from an anti-reflective material comprises forming an insulation layer including a layer selected from the group consisting of a borophosphosilicate glass (BPSG) layer, a phosphosilicate glass (PSG) layer, a borosilicate glass (BSG), an un-doped silicate glass (USG) layer, a tetra ethyl ortho silicate (TEOS) layer, a high density plasma (HDP) layer, and a silicon oxide (Si0 2 ) layer.

24. The method of claim 21 , wherein said forming an insulation layer from an anti-reflective material comprises forming an insulation layer including a layer selected from the group consisting of a silicon nitride (Si x N y ) layer, where x and y are natural numbers, and a silicon oxynitride (Si x O y N z ) layer, where x, y and z are natural numbers.

25. The method of claim 18 , wherein said forming a reflecting gate comprises forming a stacked structure of a polysilicon layer and a metal silicide layer.

26. The method of claim 18 , wherein said forming a reflecting gate comprises forming a layer of tungsten silicide.

27. The method of claim 18 , further comprising forming a transfer gate overlapping the reflecting gate.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 15, 2025
From: INTELLECTUAL VENTURES ASSETS 200 LLC
To: INTERSTATE PATENTS, LLC
Reel/Frame 073218/0509 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 18, 2025
From: INTELLECTUAL VENTURES II LLC
To: INTELLECTUAL VENTURES ASSETS 200 LLC
Reel/Frame 072049/0758 →