Method of forming dielectric layer with a dielectric composition
View Patent ↗An electronic device, such as a thin-film transistor, includes a substrate and a dielectric layer formed from a dielectric composition. The dielectric composition comprises a dielectric material and a low surface tension additive. The low surface tension additive allows for the formation of a thin, smooth dielectric layer with fewer pinholes and enhanced device yield. In particular embodiments, the dielectric material comprises a lower-k dielectric material and a higher-k dielectric material. When deposited, the lower-k dielectric material and the higher-k dielectric material form separate phases.
1. A process for fabricating an electronic device having a dielectric layer on a substrate, comprising:
depositing a dielectric composition on the substrate, the dielectric composition comprising a dielectric material and a low surface tension additive;
optionally heating the dielectric composition, forming the dielectric layer on the substrate;
wherein the low surface tension additive is a polyacrylate modified hydroxyl functional polysiloxane.
2. The process of claim 1 , wherein the low surface tension additive is present in an amount of from about 0.0001 to about 3.0 wt % of the dielectric material.
3. The process of claim 1 , wherein the dielectric composition further comprises a crosslinking agent.
4. The process of claim 1 , wherein the dielectric material comprises a lower-k dielectric material and a higher-k dielectric material, wherein the lower-k dielectric material has a dielectric constant of less than 4.0 and wherein the higher-k dielectric material has a dielectric constant of 6.0 or more.
5. The process of claim 4 , wherein the lower-k dielectric material is poly(methyl silsesquioxane); and
the higher-k dielectric material is poly(4-vinylphenol).
6. The process of claim 1 , wherein the dielectric composition further comprises a thermal acid generator or a photo acid generator.
7. The process of claim 1 , wherein the dielectric layer is substantially free of pin holes.
8. The process of claim 1 , wherein the dielectric layer has a thickness of from about 10 nm to about 1000 nm.
9. The process of claim 1 , wherein the dielectric layer has a surface roughness of less than 10 nm.