Interpolation circuitry for optical encoders
View Patent ↗Disclosed are various embodiments of circuitry and methods for generating interpolated signals in an optical encoder. The optical encoder configurations and circuitry disclosed herein permit very high resolution reflective optical encoders in small packages to be provided. Methods of making and using such optical encoders are also disclosed. According to one embodiment, the interpolated signals are generated through the use of signal generation circuitry, peak voltage generation circuitry, reference voltage generation circuitry, slope detection circuitry, and a clocked comparator that is configured to output interpolated output pulses.
1. A method of interpolating optical encoder signals, comprising:
emitting light from a light emitter towards a plurality of photodetectors or photodiodes having leading and trailing edges arranged along a single track and a common axis to form a single track light detector light detector, the single track light detector having disposed along the common axis pairs of A and A\ data channel light detectors and B and B\ data channel light detectors,
generating first, second, third and fourth output ramp signals corresponding, respectively, to the A, A\, B and B\ light detectors, the A and B light detectors, and the A\ and B\ light detectors, respectively, being arranged to generate output signals that are 90 degrees out of phase with respect to one another;
generating a peak voltage and an offset voltage corresponding to the output ramp signals, and providing the peak voltage and the offset voltage to reference voltage generation circuitry as inputs thereto;
generating, with a resistor ladder and corresponding controllable switches or a digital-to-analog converter (DAC) in the reference voltage generation circuitry, and on the basis of the peak and offset voltages, a plurality of different reference voltages including a first, second, third, and fourth reference voltage, the first, second, third, and fourth reference voltage corresponding to a predetermined angular position of the first, second, third, and fourth output ramp signals, respectively, over a predetermined range of angular positions, only one of the plurality of different reference voltages being provided at any given time as a first input to a clocked comparator;
generating, with a slope detection circuit having provided as inputs thereto the first, second, third and fourth output ramp signals, slope detection circuit output signals corresponding to the predetermined range of angular positions for each of the first, second, third and fourth output ramp signals as such angular positions occur and providing such slope detection circuit output signals as a second input to the clocked comparator, and
outputting from the clocked comparator, on the basis of the first and second inputs to the clocked comparator, interpolated output pulses.
2. The method of claim 1 , wherein the predetermined range of angular positions is 90 degrees.
3. The method of claim 1 , wherein the peak voltage is about plus or minus 1 volt and the offset voltage is about zero volts.
4. The method of claim 1 , wherein the peak voltage is about plus or minus 2 volts and the offset voltage is about one volt.
5. The method of claim 1 , wherein the reference voltage generation circuitry further comprises first and second voltage follower amplifiers disposed at opposite ends of the resistor ladder, the first voltage follower receiving a sum of the peak voltage and the offset voltage as an input thereto, the second voltage follower receiving the offset voltage as an input thereto.
6. The method of claim 1 , wherein the resistor ladder of the reference voltage generation circuitry further comprises a plurality of voltage dividers corresponding to equal increments of the predetermined range of angular positions.
7. The method of claim 6 , wherein the equal increments are 9 degrees.
8. The method of claim 1 , wherein the interpolated output pulses are provided to a divide by two counter.
9. The method of claim 1 , wherein the interpolated output pulses are provided to an up-down counter as inputs thereto.
10. The method of claim 9 , wherein an output from the up-down counter is provided to a 1-hot decoder as an input thereto.
11. The method of claim 10 , wherein the up-down counter is a 4-bit binary up-down counter that detects positive slopes of the first, second, third, and fourth output ramp signals to select the first input to the clocked comparator based on which among the first, second, third, and fourth output ramp signals has the highest rising slope and wherein outputs from the 1-hot decoder are employed to control opening and closing of the controllable switches of the resistor ladder in the reference voltage generation circuitry.
12. The method of claim 9 , wherein the up-down counter has a power-on-reset circuit connected as an input thereto.
13. An optical encoder, comprising:
a light emitter configured to emit light therefrom;
a plurality of photodetectors or photodiodes having leading and trailing edges arranged along a single track and a common axis to form a single track light detector, the single track light detector having disposed along the common axis pairs of A and A\ data channel light detectors and B and B\ data channel light detectors, the A and B light detectors, and the A\ and B\ light detectors, respectively, being arranged to generate output signals that are 90 degrees out of phase with respect to one another, the A, A\, B and B\ light detectors generating respective first, second, third and fourth output ramp signals;
signal generation circuitry comprising at least first, second, third and fourth amplifiers configured to receive as inputs thereto, respectively, the first, second, third and fourth output ramp signals corresponding to the A, A\, B and B\ light detectors, the first amplifier being configured to provide an A output ramp signal, the second amplifier being configured to an A\ output ramp signal, the third amplifier being configured to provide a B output ramp signal, the fourth amplifier being configured to a B\ output ramp signal;
peak voltage generation circuitry configured to generate a peak voltage corresponding to the output ramp signals;
reference voltage generation circuitry comprising a resistor ladder or a digital-to-analog converter (DAC) and corresponding controllable switches configured to generate on the basis of the peak and offset voltages provided as inputs thereto a plurality of different reference voltages including a first, second, third, and fourth reference voltage, the first, second, third, and fourth reference voltage corresponding to a predetermined angular position of the first, second, third, and fourth output ramp signals, respectively, over a predetermined range of angular positions, only one of the plurality of different reference voltages being provided at any given time as a first input to a clocked comparator, and
slope detection circuitry having provided as inputs thereto the first, second, third and fourth output ramp signals, and configured to generate slope detection circuitry output signals corresponding to the predetermined range of angular positions for each of the first, second, third and fourth output ramp signals as such angular positions occur, such slope detection circuitry output signals being provided as a second input to the clocked comparator;
wherein the clocked comparator is configured to output on the basis of the first and second inputs thereto interpolated output pulses.
14. The optical encoder of claim 13 , wherein the peak voltage generation circuitry is further configured to generate an offset voltage corresponding to the output ramp signals.
15. The optical encoder of claim 13 , wherein the predetermined range of angular positions is 90 degrees.
16. The optical encoder of claim 13 , wherein the peak voltage is about plus or minus 1 volt and the offset voltage is about zero volts.
17. The optical encoder of claim 13 , wherein the peak voltage is about plus or minus 2 volts and the offset voltage is about one volt.
18. The optical encoder of claim 13 , wherein the reference voltage generation circuitry further comprises first and second voltage follower amplifiers disposed at opposite ends of the resistor ladder, the first voltage follower receiving a sum of the peak voltage and the offset voltage as an input thereto, the second voltage follower receiving the offset voltage as an input thereto.
19. The optical encoder of claim 13 , wherein the resistor ladder of the reference voltage generation circuitry further comprises a plurality of voltage dividers corresponding to equal increments of the predetermined range of angular positions.
20. The optical encoder of claim 13 , wherein the equal increments are 9 degrees.
21. The optical encoder of claim 13 , wherein the interpolated output pulses are provided to a divide-by-two counter.
22. The optical encoder of claim 13 , wherein the interpolated output pulses are provided to an up-down counter as inputs thereto.
23. The optical encoder of claim 22 , wherein an output from the up-down counter is provided to a 1-hot decoder as an input thereto.
24. The optical encoder of claim 23 , wherein the up-down counter is a 4-bit binary up-down counter that detects positive slopes of the first, second, third, and fourth output ramp signals to select the first input to the clocked comparator based on which among the first, second, third, and fourth output ramp signals has the highest rising slope and wherein outputs from the 1-hot decoder are employed to control opening and closing of the controllable switches of the reference voltage generation circuitry.
25. The optical encoder of claim 22 , wherein the up-down counter has a power-on-reset circuit connected as an input thereto.