Memory circuit and method of forming the same using reduced mask steps
Disclosed is a memory circuit and method of forming the same. The memory circuit comprises a lower metallization layer defining first conducting lines. A continuous magnetic storage element stack is atop the lower metallization layer wherein a bottom electrode of the stack is in direct contact with the first conducting lines. An upper metallization layer is atop the continuous magnetic storage element stack, the upper metallization layer defining second conducting lines, which are in direct contact with said continuous magnetic storage element stack. Localized areas of the continuous magnetic storage element stack define discrete magnetic bits, each energizable through a selected pair of the first and second conducting lines. In a second aspect and a third aspect, the continuous magnetic storage element stack is respectively partially and fully etched through a single mask, to define the discrete magnetic bits.
1. A memory circuit comprising:
a lower metallization layer defining first conducting lines;
a continuous magnetic storage element stack atop said lower metallization layer wherein a bottom electrode of said continuous magnetic storage element stack is in direct contact with said first conducting lines; and
an upper metallization layer atop said continuous magnetic storage element stack, said upper metallization layer defining second conducting lines which are in direct contact with said continuous magnetic storage element stack, wherein localized areas of said continuous magnetic storage element stack define discrete magnetic bits, each energizable through a selected pair of said first and second conducting lines.
2. The memory circuit of claim 1 wherein said continuous magnetic storage element stack comprises a magnetic tunnel junction (MTJ) stack.
3. The memory circuit of claim 1 wherein said lower metallization layer comprises an M2 layer and said upper metallization layer comprises an M3 layer.
4. The memory circuit of claim 1 wherein said first conducting lines comprise a plurality of word lines and said second conducting lines comprise a plurality of bit lines.