Semiconductor device with both I/O and core components and method of fabricating same
View Patent ↗A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.
1. A method of fabricating a semiconductor device, comprising:
forming a core well in a core region of a substrate and an I/O well in an I/O region of the substrate, the core well and the I/O well separated by an isolation structure;
forming an I/O-device gate structure on the I/O well, the I/O-device gate structure comprising an I/O electrode disposed above an I/O dielectric, wherein the I/O dielectric does not include a high-k dielectric material;
forming a strained-silicon channel in the core region, wherein the strained-silicon channel comprises a silicon layer disposed on a silicon germanium layer, the silicon germanium layer disposed between the silicon layer and the substrate;
forming a core-device gate structure over the strained-silicon channel in the core well, the core-device gate structure comprising a core electrode disposed above a core dielectric, the core-device gate structure comprising a high-k dielectric material; and
forming a source region and a drain region adjacent to the core-device gate structure and outside of the silicon germanium layer.
2. The method of claim 1 , further comprising the steps of performing an LDD ion implantation into the I/O well, and annealing the semiconductor device subsequent to the LDD ion implantation.
3. The method of claim 2 , wherein the semiconductor device comprises an n-type I/O well and a p-type I/O well, and wherein the LDD ion implantation comprises a p-type LDD ion implantation and an n-type LDD ion implantation.
4. The method of claim 1 , wherein the core dielectric has a dielectric constant of greater than about 10.
5. The method of claim 1 , wherein the I/O dielectric is formed of silicon dioxide.
6. The method of claim 1 , further comprising forming a resistor disposed on an isolation structure adjacent to the core well.
7. The method of claim 6 , further comprising forming a nitride layer over the I/O-device gate structure and the resister prior to forming the strained-silicon channel.
8. The method of claim 1 , wherein the forming the strained-silicon channel further comprises:
forming a channel recess in the core well;
forming the silicon germanium layer in the channel recess by epitaxial growth; and
forming the silicon layer by epitaxial growth.
9. The method of claim 1 , further comprising implanting ions into the core well for V t (threshold voltage) adjustment.
10. The method of claim 1 , wherein the forming the source region and the drain region further comprises:
forming a source region recess and a drain region recess in the core well adjacent the core-device gate structure;
forming a silicon-germanium layer in the source region recess and in the drain region recess by epitaxial growth; and
forming a silicon-carbon layer over the silicon-germanium layer by epitaxial growth.
11. The method of claim 10 , further comprising forming sacrificial spacers along the core-device gate structure prior to the forming a source region recess and a drain region recess.
12. A method of manufacturing a semiconductor device, the method comprising:
forming an core region and an I/O region in a substrate:
forming an I/O device in the I/O region, the I/O device comprising an I/O gate electrode overlying an I/O gate dielectric, wherein the I/O gate dielectric does not include a high-k dielectric; and
forming a core device in the core region, the forming the core device comprising:
forming a strained-silicon channel region, wherein the strained-silicon channel region comprises a multi-layer stack filling a recess disposed within the core region, wherein the multi-layer stack comprises a silicon layer disposed on a silicon germanium layer, the silicon germanium layer being disposed on the substrate;
forming a core gate dielectric overlying the strained silicon channel region;
forming a core gate electrode overlying the core gate dielectric; and
forming a source region and a drain region formed outside of the strained-silicon channel region and formed on opposite sides of the core gate dielectric.
13. The method of claim 12 , wherein the forming the source region and the drain region further comprises:
forming a source region recess and a drain region recess in the core well adjacent the core gate dielectric;
forming a silicon-germanium layer in the source region recess and in the drain region recess by epitaxial growth; and
forming a silicon-carbon layer over the silicon-germanium layer by epitaxial growth.
14. The method of claim 12 , wherein the forming the strained-silicon channel region further comprises:
forming a channel recess in the core region;
forming the silicon germanium layer in the channel recess by epitaxial growth; and
forming the silicon layer by epitaxial growth.
15. The method of claim 12 , further comprising forming a resistor disposed on an isolation structure adjacent to the core region.
16. The method of claim 12 , wherein the core gate dielectric has a dielectric constant greater than about 8.
17. The method of claim 12 , further comprising performing an LDD ion implantation into the I/O region and annealing subsequent to the LDD ion implantation.
18. A method of fabricating a semiconductor device on a substrate, comprising:
forming a core well and an I/O well separated by at least one isolation structure;
forming an I/O device gate structure in the I/O well; wherein the I/O device gate structure does not include a high-k dielectric;
forming an LDD in the I/O well;
forming dummy spacers to protect the I/O device;
defining a core device channel, wherein the core device channel comprises a silicon layer over a silicon germanium layer, the silicon germanium layer disposed between the silicon layer and the substrate;
forming a core device high-k gate dielectric;
forming a core device gate electrode;
forming a core device source region and a core device drain region, the core device source region and the core device drain region located outside of the core device channel;
removing the dummy spacers; and
forming spacers for the core device and the I/O device.
19. The method of claim 18 , further comprising adjusting a V t of the core device channel by ion implantation.
20. The method of claim 18 , wherein the LDD in the I/O well is formed in the substrate.